武汉 豪威科技 招聘 数字ic设计 数字ic验证 模拟ic设计 laylout工程师

Tristone1217

武汉豪威科技诚招ic设计相关工程师有意愿的可发简历到tristone12173718@126.com，可直接内推。具体岗位如下
数字ic设计工程师
Job responsibilities：
1. Create design block architecture and micro-architecture design specification.
2. RTL design in Verilog, lint, clock domain crossing (CDC) analysis, top level integration, synthesis, timing analysis, timing closure, DFT-related tasks
3. Work with verification team on planning and execution, simulation, debugging block and system level simulations, formal verification, preparation of technical reviews and product/block documentation.
4. Interact with technical leaders of the company and senior staff in engineering, marketing, and corporate development to help ensure successful development of high value technologies and products.

Job requirements:
1. Bachelor degree or above in microelectronics, electronic information engineering or automation.
2. At least 5 years’ experience in chip related digital circuit design.
3. Familiar with Verilog language, familiar with the transformation from algorithm to RTL.
4. Familiar with Logic Synthesis, Static Timing Analysis.
5. Understand the basic flow of digital APR.

数字IC验证工程师
岗位职责
1、负责芯片中数字模块及系统级验证工作；
2、依据数字设计spec撰写验证文档；
3、依据验证文档撰写testcase并能够仿真发现并反馈问题；
4、参与芯片的样品调试和量产测试.；
5、参与从RTL到GDSII的全部芯片开发流程，在各个阶段提供支持，推动项目顺利完成。

任职要求：
1、本科以上学历，电子工程，微电子，或相关专业；
2、3年以上数字电路设计、验证经验；
3、熟悉ASIC 流程，熟悉Verilog；
4、数字电路基础知识扎实，学习能力强；
5、熟悉UVM/VMM验证方法学，并能够独立搭建模块级的验证平台
6、有成功产品完整开发和流片经历者优先。


模拟IC设计工程师
职位描述
1、配合市场部完成项目的评估，参与制定模拟电路芯片的设计规范；
2、根据模拟芯片设计规范设计芯片系统模块及电路架构，以及系统仿真、验证；
3、根据芯片模块设计晶体管级电路，设计、仿真、验证各模块；
4、规划版图布局，指导和协助版图工程师完成版图设计，确保版图***程度发挥电路的性能，并完成电路的后仿真；
5、指导测试工程师完成芯片的测试验证，主导芯片的debug工作；
6、协助测试工程师制定测试规范和解决测试开发中的问题；
7、配合应用和产品工程师，测试工程师使产品成功进入量产；
8、配合应用和现场工程师解答客户技术问题，配合解决客户端应用问题。

岗位要求：
1、微电子学/集成电路相关专业，硕士研究生及以上学历；
2、熟悉半导体物理和器件原理，熟悉集成电路CMOS/BCD工艺、熟悉集成电路版图、熟悉ESD防护的原理；
3、精通模拟集成电路设计，熟悉数字电路原理，熟悉常用的模拟模块和数字电路模块的结构；
4、精通开关电源特别是DC-DC的原理与架构，拥有开关电源IC的流片、Debug和量产经验；
5、熟练使用Linux操作系统，并能熟练使用主流的EDA工具进行设计和仿真；
6、具有良好的中英文阅读、沟通和文档写作能力；
7、工作积极主动、吃苦耐劳，具有良好的学习能力、沟通能力和团队合作精神。


系统验证工程师
Job Responsibilities:
1. Deeply study of OLED DDIC product requirement, design documents, FW design documents, JEDEC spec and SERDES characterization spec, then define the test strategy, develop the test plans for full coverage.
2. System validation test case implementation for different validation phase: FW testing, MCU features validation, data path validation, functional coverage validation, and customer/OEM testing.
3. Test execution and management per test plan on different hardware platform: Virtual platform, HW emulator, FPGA platform and real panel. Analyzing test results. FW, SoC, HW system issue debugging.
4. Work closely with FW engineer, AISC design engineer, hardware system design engineer, to solve issues to meet initial design system requirements.
5. Develop and enhance the system validation automation framework, optimize validation methodology to shorten the validation cycle and enhance the validation coverage.
6. Support architecture and design team for definition of future products ‘requirements.

Requirements:
1. Bachelor degree or above, major in electronics, 3 years working experience or above
2. Familiar with MCU and C/C++ program;
3. Familiar with SPI, I2C interface and spi-flash, EEPROM devices;
4. Familiar with MIPI interface protocol, experience in display industry is preferred;
5. Familiar with Verilog and FPGA development experience is preferred;
6. Be able to read technical documents in English.


版图设计工程师
Position Overview:　
Responsible for IC full-custom analog layout, verification of the layout (DRC/ERC/LVS), RC extraction for post simulation
Responsibilities:　
Primary (70%):
1.Full custom analog layout/verification and RC extraction.
2.Perform block level layout. Conduct physical verification (DRC and LVS using Cadence tools).

Secondary (30%):
1.Team work with analog designers, optimize layout.
2.Perform floor planning and placements (pad locations and custom routing).

Requirements:　
1.Bachelor or above degree with 5 years experiences in CMOS IC full-custom layout.
2.Experiences in Mixed signal/analog/high speed layout.
3.Familliar with layout skills and knowledge is must.
4.Good teamwork/communication/positive is must.
5.Familiar with Cadence IC layout and verification tools
6.Having massive IP block experience
Plus:
1.Familiar with 0.18/0.13/0.09/0.065/0.04 um CMOS process and design rule is a plus.
2.Familiar with ESD/Latch up/antenna and related layout solutions is a plus.
3.Familiar with layout size reduction is a plus, with standard cell experience is good.
4.Familiar with rule deck is a plus.