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请问一下,如何在rtl的子模块bind一个interface
我的代码如下://接口文件
`ifndef MY_IF__SV
`define MY_IF__SV
interface my_bind_if(input clk);
logic [7:0] in1;
logic [7:0] in2;
logic [8:0] out1;
endinterface
`endif
//top_tb文件
bind adder8 my_bind_if my_bind_if_inst(
.in1(a_i),
.clk(clk),
.in2(b_i),
.out1(c_o)
);
//rtl模块
module dut(clk,
rst_n,
rxd,
rx_dv,
txd,
tx_en);
...
adder8 add_inst(
.clk(clk),
.a_i(rxd),
.b_i(rxd),
.c_o(result)
);
vcs仿真的报错信息为:
Error-[UPIMI-E] Undefined port in module instantiation
top_tb.sv, 25
Port "in1" is not defined in interface 'my_bind_if' defined in "my_if.sv",
10
Interface instance: my_bind_if my_bind_if_inst( .in1 (a_i), .clk (clk),
.in2 (b_i), .out1 (c_o));
Error-[UPIMI-E] Undefined port in module instantiation
top_tb.sv, 25
Port "in2" is not defined in interface 'my_bind_if' defined in "my_if.sv",
10
Interface instance: my_bind_if my_bind_if_inst( .in1 (a_i), .clk (clk),
.in2 (b_i), .out1 (c_o));
Error-[UPIMI-E] Undefined port in module instantiation
top_tb.sv, 25
Port "out1" is not defined in interface 'my_bind_if' defined in "my_if.sv",
10
Interface instance: my_bind_if my_bind_if_inst( .in1 (a_i), .clk (clk),
.in2 (b_i), .out1 (c_o));
请问该如何解决呢
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