Anantha关于低功耗的经典文献:minimizing power consumption in CMOS circuits

grantEE · 发表于 2007-12-6 16:10:28

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Minimizing Power Consumption in CMOS Circuits

Anantha P. Chandrakasan
Robert W. Brodersen

Department of EECS
University of California at Berkeley

grantEE · 发表于 2007-12-6 16:11:55

Abstract: An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important
technology consideration is the threshold voltage and its control which allows the reduction of supply voltage without significant impact on logic speed. Even further supply reductions can be made by the use of an architecture based voltage scaling strategy, which uses parallelism and pipelining, to trade-off silicon area and power reduction. Since energy is only consumed when capacitance is being switched,
power can be reduced by minimizing this capacitance through operation reduction, choice of number representation, exploitation of signal correlations, re-synchronization to minimize glitching, logic design, circuit design and physical design. The low-power techniques that are presented have been applied to the design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and fullmotion
video. The entire chipset that performs protocol conversion, synchronization, error correction, packetization, buffering, video decompression and D/A conversion operates from a 1.1V supply and consumes less than 5mW.

grantEE · 发表于 2007-12-6 16:13:43

References
[1] N. Weste and K. Eshragian, Principles of CMOS VLSI Design: A Systems Perspective, Addison-Wesley, MA, 1988.
[2] H.J.M. Veendrick, ‘‘Short-Circuit Dissipation of Static CMOS Circuitry and Its Impact on the Design of Buffer Circuits’’,
IEEE Journal of Solid-State Circuits, Vol. SC-19, pp. 468-473, August 1984.
[3] T. Burd, “ Low-power CMOS Library Design Methodology”, Masters thesis, ERL U.C. Berkeley, June 1994.
[4] A. Stratakos, S. Sanders, R. Brodersen, “A Low-voltage CMOS DC-DC Converter for a Portable Low-Powered Battery-
Operated System,” in Proc. IEEE Power Electronics Specialists Conference, 1994.
[5] A. Shen, A. Ghosh, S. Devedas, K. Keutzer, “On Average Power Dissipation and Random Pattern Testability of
CMOS Combinational Logic Networks”, Proc. IEEE ICCAD, pp. 402-407, 1992.
[6] J. Monteiro, S. Devadas, A. Ghosh, “Retiming Sequential Circuits for Low Power”, IEEE International Conference on
Computer-Aided Design, pp. 398-402.
[7] V. Tiwari, P. Ashar, S. Malik, “Technology Mapping for Low Power”, pp. 74-79, proceedings of the 1993 Design
Automation conference.
[8] C. Tsui, M. Pedram, A. Despain, “Technology Decomposition and Mapping Targeting Low Power Dissipation”,
pp.68-73, proceedings of the 1993 Design Automation conference.
[9] M. Alidina, J. Monterio, S. Devadas, A. Ghosh, M. Papaefthymiou, “Precomputation-Based Sequential Logic Optimization
for Low Power”, 1993 International Workshop in Low Power Design.
[10] J. Yuan and C. Svensson, “High-Speed CMOS Circuit Technique”, IEEE Journal of Solid-state Circuits, pp. 62-70,
February 1989.

grantEE · 发表于 2007-12-6 16:14:45

[11] H.B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, Menlo Park, CA, 1990.
[12] M. Kakumu and M Kinugawa, “Power-Supply Voltage Impact on Circuit Performance for Half and Lower Submicrometer
CMOS LSI”, IEEE Transactions on Electron Devices, Vol 37, No. 8, pp. 1902-1908, August 1990.
[13] D. Dahle, “Designing High Performance Systems to Run from 3.3V or Lower Sources”, Silicon Valley Personal
Computer Conference, pp. 685-691, 1991.
[14] A. P. Chandrakasan, S. Sheng, R.W. Brodersen, “Low-Power CMOS Digital Design,” IEEE Journal of Solid-State
Circuits, Vol. 27, No. 4, pp. 473-484, April 1992.
[15] P. E. Landman, J. M. Rabaey, “Power Estimation for High Level Synthesis,” Proceedings of EDAC ‘93, Paris, Feb.
1993, pp. 361-366.
[16] A. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, R. Brodersen, “Minimizing Power Using Transformations”,
Submitted to IEEE Transactions on CAD, March 1993.
[17] K.K. Parhi: “Algorithm Transformation Techniques for Concurrent Processors”, Proc. of the IEEE, Vol. 77., No. 12,
pp. 1879-1895.
[18] A. Gersho, R. Gray, Vector Quantization and Signal Compression, Kluwer Academic Publishers, 1992.
[19] W.C. Fang, C.Y. Chang, B.J. Sheu,"A Systolic Tree-Searched Vector Quantizer for Real-Time Image Compression,"
VLSI signal processing IV, New York: IEEE Press, 1990.
[20] A. P. Chandrakasan, A. Burstein, R.W. Brodersen, “A Low-power Chipset for Portable Multimedia Applications,”
proceedings of the IEEE International Solid State Circuits Conference, Feb. 1994.