【NVIDIA英伟达】Mask Layout Design Engineer -上海

NVHR

NVIDIA 热招 Mask Design Engineer -上海

简历投递: tracyw@nvidia.com  微信: 1751315121

全员持股+周末双休+965+补充公积金+补充商业医疗保险

职位关键词: IP Layout

Job Description
We are now looking for Mask Design Engineer for Digital IP team. The team develops the high performance digital IPs used in our chips. The main role is layout design for SRAM, ROM and STDcell using the most advanced IC process in the world.

What you’ll be doing:
Develop digital IP layouts with excellent PPA in the most advanced process node
Verify the layout in cell level and macro level
Maintain the layouts per requests from circuit designers or other internal customers
Create tools or scripts to improve work efficiency

What we need to see:
BS/MS in EE or equivalent experience
Fundamental knowledge in digital logic, semiconductor device and manufacturing process
Minimum 1 years working experience on digital or mixed-signal layout design
Familiar with Cadence design environment and ICV/Calibre verification tools
Excellent communication in English

Ways to stand out from the crowd:
Experience on Standard Cell or SRAM layout design
Experience on layout design in 16/14nm node and beyond
Knowledge in place and route
Proficient user of Skill or Perl

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.