2020-The Fourth Terminal-Benefits of Body-Biasing Techniques for FDSOI Circuits and Systems

hdzwx1983

The CMOS integration race has reached limitations for planar silicon process
starting from the 40 nm node. The transistor channel was more and more difficult to
control and specific process integration methods such as pocket implant, silicon
strain, and lightly doped drain were introduced to enable devices’ good carrier
mobility and electrostatic control, are moreover this type of process integration
could not be successfully continued after the 20nm node. Starting from the 28nm
node a consensus solution emerged consisting in the use of fully depleted active
devices either fully depleted silicon on insulator (FD-SOI) or Fin-FET. While the
fundamental physics laws are similar for these two big families of devices, the
process integration is much different and had to bring the process engineers from
the well-known planar technologies (applies also for FD-SOI) to fully 3D structures
(for Fin-FET).

AlexKe

谢谢分享

waley

3q3q~~

student321

thanks

xiaofuss_

感谢

lhyi

Thank you for sharing

icroad

资料不错，多谢分享

dennates

thanks

MustafaSami

Thanks for sharing, great technology especially for programmable current sources

cdting

Thanks!!!