VLSI Architecture Tomasulo Algorithm

udaisai4148

Code implemented to take care of RAW WAW WAR hazards:
Can be debugged with machine-level RISC V code
Three Stages of Tomasulo Algorithm 1.Issue—get instruction from FP Op Queue If reservation station free (no structural hazard), the scoreboard issues instr & sends operands (renames registers).
2.Execution—operate on operands (EX) When both operands ready then execute; if not ready, watch CDB for result
3.Write result—finish execution (WB) Write on Common Data Bus to all awaiting units; mark reservation station available
• Normal bus: data + destination
Common Data Bus: data + source:
Normal = “Go To” bus; CDB = “Come From” bus

xiaofuss111

感谢

neilsu

Thanks for sharing.

tu_yjq123

多谢分享

dcircuit

kankan

AlexKe

Thanks

cdting

Thanks!!