(12月4日增加3本)【Springer丛书系列】SERIES ON INTEGRATED CIRCUITS AND SYSTEMS

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-Book:
"System-level Test and Validation of Hardware/Software Systems"
-Content:
========================================================
1 Introduction
Z. Peng, M. Sonza Reorda and M. Violante......................................................1
Acknowledgments.............................................................................................3
2 Modeling Permanent Faults
J.P. Teixeira......................................................................................................5
2.1 Abstract .....................................................................................................5
2.2 Introduction ...............................................................................................5
2.3 Definitions.................................................................................................8
2.4 High-level Quality Metrics........................................................................9
2.5 System and Register-transfer-level Fault Models for Permanent Faults .12
2.5.1 Observability-based Code Coverage Metrics................................15
2.5.2 Validation Vector Grade ...............................................................15
2.5.3 Implicit Functionality, Multiple Branch........................................17
2.6 Conclusions .............................................................................................22
Acknowledgments...........................................................................................23
References.......................................................................................................23
3 Test Generation: A Symbolic Approach
F. Fummi and G. Pravadelli ...........................................................................27
3.1 Abstract ...................................................................................................27
3.2 Introduction .............................................................................................27
3.3 Binary Decision Diagrams ......................................................................29
3.4 Methodology ...........................................................................................30
3.4.1 The Random-based Approach.......................................................31
3.4.2 The Symbolic Approach ...............................................................31
3.4.3 Hardware Design Language to Binary Decision Diagram Translation
................................................................................................32
3.4.4 Functional Vector Generation for a Single Process ......................32
3.4.5 Functional Vector Generation for Interconnected Processes ........33
3.5 The Testing Framework ..........................................................................33
3.5.1 Fault Model Definition..................................................................35
3.5.2 Automatic Test Pattern Generation Engines .................................41
3.6 Experimental Results ..............................................................................43
3.7 Concluding Remarks ...............................................................................44
Acknowledgments...........................................................................................45
References.......................................................................................................45
4 Test Generation: A Heuristic Approach
O. Goloubeva, M. Sonza Reorda and M. Violante..........................................47
4.1 Abstract ...................................................................................................47
4.2 Introduction.............................................................................................47
4.3 Assumptions............................................................................................50
4.4 High-level Test Generation .....................................................................50
4.4.1 High-level Fault Models ...............................................................50
4.4.2 High-level Test Generation...........................................................51
4.5 Testing Hardware/Software Systems ......................................................52
4.5.1 testgen Results ..............................................................................54
4.5.2 Results Starting from Random Vectors.........................................55
4.5.3 Results Starting from Designer Vectors........................................55
4.5.4 Result Discussion..........................................................................56
4.6 Validating Application-specific Processors ............................................56
4.6.1 Design Flow..................................................................................58
4.6.2 Experimental Results ....................................................................60
4.6.3 Results of the Processor Customization........................................61
4.6.4 Results of the Test Vector Generation ..........................................61
4.7 Conclusions.............................................................................................63
References.......................................................................................................64
5 Test Generation: A Hierarchical Approach
G. Jervan, R. Ubar, Z. Peng and P. Eles ........................................................67
5.1 Abstract ...................................................................................................67
5.2 Introduction.............................................................................................67
5.3 Modeling with Decision Diagrams .........................................................68
5.3.1 State of the Art ..............................................................................68
5.3.2 Modeling Digital Systems by Binary Decision Diagrams ............69
5.3.3 Modeling with a Single Decision Diagram on Higher Levels ......71
5.4 Hierarchical Test Generation with Decision Diagrams...........................73
5.4.1 Scanning Test................................................................................74
5.4.2 Conformity Test ............................................................................78
5.5 Conclusions.............................................................................................80
References.......................................................................................................81
6 Test Program Generation from High-level Microprocessor Descriptions
E. Sánchez, M. Sonza Reorda and G. Squillero ..............................................83
6.1 Abstract ...................................................................................................83
6.2 Introduction.............................................................................................83
6.3 Microprocessor Test-program Generation ..............................................85
6.4 Methodology Description........................................................................87
6.4.1 Architectural Models ....................................................................89
6.4.2 Register-transfer-level Models......................................................90
6.5 Case Study ..............................................................................................94
6.5.1 Processor Description ...................................................................94
6.5.2 Automatic Tool Description..........................................................96
6.5.3 Experimental Setup .......................................................................98
6.6 Experimental Results ..............................................................................99
6.6.1 High-level Metrics Comparison..................................................103
6.7 Conclusions ...........................................................................................104
Acknowledgments.........................................................................................105
References.....................................................................................................105
7 Tackling Concurrency and Timing Problems
I.G. Harris.....................................................................................................107
7.1 Abstract .................................................................................................107
7.2 Introduction ...........................................................................................107
7.3 Synchronization Techniques .................................................................109
7.4 A Class of Synchronization Errors........................................................111
7.5 A Fault Model for Synchronization Errors............................................113
7.5.1 Detection of Synchronization Faults ...........................................114
7.5.2 Fault Coverage Computation ......................................................115
7.6 Experimental Results ............................................................................116
7.7 Conclusions ...........................................................................................118
Acknowledgments.........................................................................................118
References.....................................................................................................118
8 An Approach to System-level Design for Test
G. Jervan, R. Ubar, Z. Peng and P. Eles ......................................................121
8.1 Abstract .................................................................................................121
8.2 Introduction ...........................................................................................121
8.3 Hybrid Built-in Self-test........................................................................123
8.3.1 Hybrid Built-in Self-test Cost Optimization ...............................126
8.4 Hybrid Built-in Self-test for Multi-core Systems ..................................129
8.4.1 Built-in Self-test Time Minimization for Systems with Independent
Built-in Self-test Resources ..................................................130
8.4.2 Built-in Self-test Time Minimization for Systems with Test Pattern
Broadcasting ...............................................................................139
8.5 Conclusions ...........................................................................................146
References.....................................................................................................147
9 System-level Dependability Analysis
A. Bobbio, D. Codetta Raiteri, M. De Pierro and G. Francheschinis...........151
9.1 Abstract .................................................................................................151
9.2 Introduction ...........................................................................................151
9.3 Introduction to Fault Trees....................................................................153
9.3.1 Fault Tree Example.....................................................................154
9.3.2 Modeling Dependencies in the Failure Mode Using
Dynamic Gates............................................................................155
9.3.3 Giving a Compact Representation of Symmetric Systems
through Parameterization ............................................................156
9.3.4 Modeling the Repair Process Through the Repair Box...............158
9.4 Reliability Analysis...............................................................................159
9.4.1 Qualitative Analysis....................................................................159
9.4.2 Quantitative Analysis..................................................................160
9.4.3 Importance Measures ..................................................................161
9.5 Qualitative and Quantitative Analysis of the Examples........................163
9.5.1 Minimal Cut-sets Detection ........................................................163
9.5.2 Quantitative Analysis..................................................................164
9.6 Conclusions...........................................................................................171
Acknowledgments.........................................................................................172
References.....................................................................................................172

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