Verification Methodology Manual for System Verilog (SystemVerilog)

cfriend · 发表于 2007-12-1 01:03:02

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Verification Methodology Manual for System Verilog (SystemVerilog)
by
Janick Bergeron, Eduard Cerny, Alan Hunter, Andrew Nightingale

The Verification Methodology Manual for SystemVerilog is a blueprint for system-on-chip (SoC) verification success. The book documents advanced functional verification techniques used by industry experts to validate complex SoCs. It describes how to use the industry-standard SystemVerilog language to create comprehensive verification environments using coverage-driven, constrained-random and assertion-based techniques, and specifies verification library building blocks for interoperable verification components.

DownloadLink: http://rapidshare.com/files/73249473/Verification_Methodology_-_Manual_for_SystemVerilog_-_Bergeron__Cerny__Hunter__Nightingale.rar

benemale · 发表于 2007-12-1 09:51:59

免费的要顶~~~~~~~~

cfriend · 发表于 2007-12-5 19:06:20

免费下载，欲下从速

DSUN · 发表于 2008-1-13 22:49:29

好东东

zjfu99 · 发表于 2008-7-11 13:41:01

好東西，似乎沒法下

cancerzero · 发表于 2009-1-20 10:21:25

好书啊，我下了，谢谢！

Verification Methodology Manual for System Verilog (SystemVerilog)

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