大咖帮我看看sdc的生成时钟约束，PT做STA总是报错

helimpopo

PT老是报错，说：Generated clock 'CLKOUT' has no path to its master clock.
sdc约束设置如下：
create_clock [get_ports EXTAL] -name EXT_CLK -period 10 -waveform {0 10}
create_generated_clock [get_pins control/clockgating/mux/Y] -name CLKOUT -source [get_ports EXTAL] -master_clock EXT_CLK -divide_by 1 -add

其实从port到EXT_CLK其实还有个mux
从EXT_CLK到CLKOUT有4个反相器，15个BUF，一个门控时钟，一个MUX2


请大神指点一下，应该怎么设置？

phoenixson

-combinational 试试 ，不用-divide_by 1

helimpopo

phoenixson 发表于 2020-7-17 17:54
-combinational 试试 ，不用-divide_by 1

一样的问题。。。

helimpopo

1. [Timing 38-249] Generated clock O has no logical paths from master clock clk_200_MHz.
   
2. [~~~/ip/fifo_async_32x1k_fwft/fifo_async_32x1k_fwft/fifo_async_32x1k_fwft_clocks.xdc:59]
   
3. 
   
4. Resolution: Review the path between the master clock and the generated clock with the schematic viewer and
   
5. correct the -source option. If it is correct and the master clock does not have a timing path to the generated
   
6. clock, define the generated clock as a primary clock by using create_clock.
   

复制代码

只有直接使用create_clock了。

胡了

可能是路径上经过一些cell，导致钟不能传递

ywwuyifan

EXT_CLK到CLKOUT中间的那个mux output也定一个generated clock然后CLKOUT source定在中间那颗mux上呢？

才看到是2020年的帖子

15909834256

master clock EXT_CLK 和source clock的名字差异导致的吗