做DC综合时出现Error: Width mismatch on port

SuperLYL · 发表于 2020-4-21 00:35:20

本帖最后由 SuperLYL 于 2020-4-21 00:36 编辑

小弟我的设计需要3个SRAM，于是我用SMIC的Memory Compiler生成了三个SRAM，分别是SRAM_1、SARM_2、SRAM_3，然后在我的设计中例化了这三个SRAM。（使用工艺是SMIC的130nm工艺）
然后rtl sim是没有问题的，做到综合的时候出现如下报错：
Error: Width mismatch on port 'A' of reference to 'SRAM_2' in 'RSA'. (LINK-3)
Error: Width mismatch on port 'D' of reference to 'SRAM_2' in 'RSA'. (LINK-3)
Error: Width mismatch on port 'CEN' of reference to 'SRAM_2' in 'RSA'. (LINK-3)
Error: Width mismatch on port 'WEN' of reference to 'SRAM_2' in 'RSA'. (LINK-3)
Warning: Unable to resolve reference 'SRAM_2' in 'RSA'. (LINK-5)
Error: Width mismatch on port 'A' of reference to 'SRAM_3' in 'RSA'. (LINK-3)
Error: Width mismatch on port 'D' of reference to 'SRAM_3' in 'RSA'. (LINK-3)
Error: Width mismatch on port 'CEN' of reference to 'SRAM_3' in 'RSA'. (LINK-3)
Error: Width mismatch on port 'WEN' of reference to 'SRAM_3' in 'RSA'. (LINK-3)
Warning: Unable to resolve reference 'SRAM_3' in 'RSA'. (LINK-5)
Link with error!

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我的SRAM_2和SRAM_3的大小都是一样的，如下（截取部分）：
module SRAM_2 (
                        Q,
                        CLK,
                        CEN,
                        WEN,
                        A,
                        D);

  parameter       Bits = 32;
  parameter       Word_Depth = 128;
  parameter       Add_Width = 7;

  output [Bits-1:0]             Q;
  input                                  CLK;
  input                                  CEN;
  input                                  WEN;
  input       [Add_Width-1:0]       A;
  input       [Bits-1:0]                D;

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例化方式如下：
SRAM_2 MEM0(r_data0, CLK, ~MemCon0[7], ~MemCon0[8], MemCon0[6:0], w_data);
SRAM_3 MEM1(r_data1, CLK, ~MemCon1[7], ~MemCon1[8], MemCon1[6:0], w_data);

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端口位置都接对了，RTL仿真是对的。
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麻烦大神们看看这个报错如何解决，救救我的设计，谢谢。