- Build digital verification test bench with UVM method, which can work at block level or whole chip level.
- Build analog verification test bench with mix simulation method for timing and power check,which can work at whole chip level
- Build coverage metrics for DRAM products based on external/internal specifications.
- Develop new methodologies for DRAM verifications by using Verilog/System Verilog/Python/Perl/C++ languages, and be capable to do the second developments based on the 3rd vendor tools.
- Develop patterns and regressions to increase the function coverage for all DRAM architectures and features.
- Build new methods and flows to guide DRAM chip design from verification view.
- Co-work with international colleagues on developing new verification tools/flows for the verification difficulties on DRAM chip.