分享一本关于电迁移的书：Electromigration Inside Logic Cells Modeling, Analyzing and Mitigating Signal Ele...

Shangkui · 发表于 2020-3-19 00:40:02

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

您需要登录才可以下载或查看，没有账号？注册

x

本帖最后由 Shangkui 于 2020-3-21 21:39 编辑

目录
Electromigration Inside Logic Cells
Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS

Contents
1 Introduction .................................................................. 1
1.1 Reliability and Electromigration ....................................... 2
1.2 Electromigration in Future Technologies .............................. 3
1.3 Motivation and Contributions .......................................... 5
1.4 Monograph Outline ..................................................... 10
2 State of the Art ............................................................... 11
2.1 Mitigating the EM Effects in Different IC Design Flow Stages ...... 11
2.1.1 Managing Electromigration in Logic Designs................. 13
2.1.2 Electromigration Impact in Future Technologies ............. 15
2.1.3 Smart Non-default Routing for Clock Power Reduction...... 16
2.1.4 Impacts of Electromigration Awareness ....................... 17
2.2 Mitigating the EM Effects in Different Types of Interconnections ... 20
2.2.1 TSVs ............................................................ 20
2.2.2 Power Delivery Network ....................................... 21
2.2.3 Clock Network .................................................. 23
2.2.4 Vias .............................................................. 24
2.2.5 Signal Interconnects ............................................ 26
2.2.6 Cell-Internal EM ................................................ 27
2.3 Summary of Related Works ............................................ 30
2.4 Conclusions ............................................................. 31
3 Modeling Cell-Internal EM ................................................. 33
3.1 Modeling Time-to-Failure Under EM.................................. 33
3.2 Joule Heating ............................................................ 35
3.2.1 Local Hot Spots from Joule Heating ........................... 36
3.3 Current Divergence ..................................................... 37
3.3.1 New Electromigration Validation: Via Node
Vector Method .................................................. 37
3.3.2 Applying Current Divergence in the Proposed EM Model ... 40
3.3.3 The Impact of Blech Length on Cell-Internal Interconnects.. 42
3.4 Conclusions ............................................................. 42


4 Current Calculation .........................................................	45
4.1 Current Flows Using Graph Traversals ................................	48

4.2 Algebra for Average/RMS Current Updates ........................... 50
4.2.1 Algebra for Computing Average Current ...................... 51
4.2.2 Algebra for Computing the RMS Current ..................... 52
4.3 Results ................................................................... 57
5 Experimental Setup .......................................................... 59
6 Results ......................................................................... 63
6.1 The Electromigration Effects for Different Logic Gates .............. 81
6.1.1 NAND2_X2 and NOR2_X2 Gates ............................ 82
6.1.2 AOI21_X2....................................................... 85
6.1.3 NOR2_X4 ....................................................... 87
6.1.4 INV_X16 ........................................................ 88
6.2 Conclusion .............................................................. 91
7 Analyzing the Electromigration Effects on Different Metal
Layers and Different Wire Lengths ........................................ 93
7.1 Experimental Setup ..................................................... 94
7.2 Simulation Results ...................................................... 95
7.3 Conclusion .............................................................. 98
8 Conclusions ................................................................... 99
8.1 Future Works ............................................................ 100
A Impact on Physical Synthesis Considering Different
Amounts of Instances with EM Awareness................................ 103
B Coupling Capacitance Currents ............................................ 111
References ..................................................................... 113