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本帖最后由 春日的白玫瑰 于 2020-2-18 16:57 编辑
岗位描述: * Work with Architecture and Software teamsto ensure micro-architecture and design is fully verified/validated acrossmultiple platforms * Define testplan for specific block leveldesign and execute the tesplan to achieve function verfication closure * Development of reusable block level UVMverification enviroment with checker/monitor/driver etc,
岗位要求: * Masters degree desired, Bachelor's degreein CS/EE is required. 3+ years of relevant experience in ASIC verificationfield. * Should have the test plan definition andexecution experience * Fluent in System Verilog and scriptinglanguages such as Python or Perl. * Must have intimate knowledge of UVMmethodology. * Experience in the verification of SoC andIO IPs such as PCIE, DDR, and peripherals such asUART/SPI/I2C/GPIO/TIMER/WATCHDOG etc. * Knowledgeable about assertions andfunctional coverage * Experience with code coverage, formalverification tools; familiarity with evolving verification methodologies. * Experience with ARM based C/Assembllytest is a big plus
有不少名额在招聘,欢迎咨询。
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