(11月30日增加12本)★好书大放送——Springer丛书系列★EE，CS & DSP★

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SEMICONDUCTOR MODELING For Simulating Signal, Power, and Electromagnetic Integrity
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CONTENTS:
PARTI: INTRODUCTION 1
1 How the Workplace Supports Successful Design 3
1.1 High-Speed Digital Design Is Challenging 3
1.2 Needs for Technical Specialization 6
1.3 The Role of Processes and Procedures 7
1.4 Using Judgment When Making Design Tradeoffs 8
1.5 HSDD Needs the Help of EDA Tools 9
1.6 HSDD Needs a Team That Extends Beyond the Company 9
1.7 HSDD Team Members Often Have Their Own Agendas 10
1.8 HSDD Simulations Performed in the Workplace 11
1.9 Modeling and Simulation Versus Prototype and Debug 12
1.10 Ten Tips for Modeling and Simulation 13
1.11 Summary 13
2 Introduction to Modeling Concepts 15
2.1 Modeling and Simulation for All Scales of System Size 15
2.2 Communicating Across Specialties 15
2.3 What Is a Model? 16
2.4 What Is a System? 18
2.5 Needs for Model Accuracy Change as a Design Progresses.... 20
2.6 There Are Many Kinds of Models and Simulations 22
2.7 Modeling and Simulation for Systems 23
2.8 Bottom-Up and Top-Down Design 24
2.9 Analog Issues in Digital Design 27
2.10 Noise Modeling on Electrical Signals 34
2.11 Additional Design Issues to Model and Simulate 36
2.12 Using EDA Tools for Semiconductors 41
2.13 Using EDA Tools for Board Interconnections 43
2.14 Looking Ahead in the Book 45
2.15 Summary 45
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PART 2: GENERATING MODELS 47
3 Model Properties Derived from Device Physics Theory 49
3.1 Introduction 49
3.2 Why Deep Sub-Micron Technology Is Complex 50
3.3 Models Extracted from Semiconductor Design Theory 52
3.4 Example of the BJT Process 53
3.5 How BJT and FET Construction Affect Their Operation 54
3.6 Calculating Device Physics Properties 65
3.7 Examples of Computing Electrical Properties from Structure. 71
3.8 Examples of SPICE Models and Parameters 75
3.9 Modeling Packaging Interconnections 90
3.10 Summary 93
4 Measuring Model Properties in the Laboratory 95
4.1 Introduction to Model Measurements 95
4.2 Matrix Models 97
4.3 Scattering-Parameter Models 103
4.4 SPICE Models 106
4.5 IBIS Models 114
4.6 Web Sites for IBIS Visual Editors and Other Tools 126
4.7 TDR/TDT - VNA Measurements 126
4.8 RLGC Matrixes 127
4.9 Field Solver RLGC Extraction for ICs 130
4.10 What is Model Synthesis? 130
4.11 Test Equipment Providers 130
4.12 Software for Test Equipment Control 131
4.13 Summary 132
5 Using Statistical Data to Characterize Component Populations 133
5.1 Why Process Variation Is Important 133
5.2 Achieving Process Control with Population Statistics 133
5.3 Basics of Population Statistics 134
5.4 Characterization for Six-Sigma Quality 144
5.5 Six-Sigma Quality for Modeling and Design 149
5.6 Summary 150

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PART 3: SELECTING COMPONENTS AND THEIR MODELS 151
6 Using Selection Guides to Compare and Contrast Components 153
6.1 Tools for Making Component Choices 153
6.2 Team Members Use of Selection Guides 155
6.3 Selection Guide Examples 156
6.4 Selection Guides Help Component Standardization 161
6.5 Simulation as a Selection Guide 161
6.6 Right-Thinking 166
6.7 Summary 167
7 Using Data Sheets to Compare and Contrast Components 169
7.1 Data Sheets as Product Descriptions 169
7.2 Are Data Sheets Accurate and Complete? 173
7.3 Selecting a Component That Is Fit for Use 175
7.4 Using Data Sheets to Begin the Selection Process 176
7.5 Construction Characteristics of Amplifiers and Switches 178
7.6 Using Beta to Explain Device Tradeoffs 179
7.7 Comparing Five BJTs to Illustrate Making a Selection 182
7.8 Process for Making Tradeoffs 195
7.9 Additional Choices for Picking a Component 197
7.10 Thoughts About the Physical Design Examples 197
7.11 Summary 198
8 Selecting the Best Model for a Simulation 199
8.1 From Component Choice to Model Choice 199
8.2 Questions That Modeling and Simulation Can Answer 200
8.3 Types of Models 201
8.4 Using Symbols and Schematics to Represent Models 202
8.5 Major Types of Models 205
8.6 Compare Models by Simulation Performance 211
8.7 Additional Model Comparisons 221
8.8 Recommendations for Modeling 223
8.9 Converting a Model to Another Type of Model 227
8.10 Transform Models for Systems 234
8.11 Summary 241
9 Modeling and Simulation in the Design Process Flow 243
9.1 Simulation in the Design Process 243
9.2 A Typical Design Flow 244
9.3 Strategy of Modeling and Simulation in Design 248
9.4 Acquiring IBIS Models: An Overview 249
9.5 Summary 257
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PART 4: ABOUT THE IBIS MODEL 259
10 Key Concepts of the IBIS Specification 261
10.1 Introduction 261
10.2 IBIS Specification 264
10.3 Sample IBIS Data File 283
10.4 Parsing and Checking IBIS Data Files 294
10.5 Schematic of a Basic IBIS Model 297
10.6 How IBIS Circuit Modeling Methodology Is Used 301
10.7 IBIS Test Circuits 309
10.8 ISO 9000 Process Documentation for IBIS Models 310
10.9 Summary 314
11 Using IBIS Models in What-If Simulations 315
11.1 A New Method of Design and Development 315
11.2 Virtual Experiments 316
11.3 Virtual Experiment Techniques 316
11.4 Propagation Delay in High-Speed Nets 317
11.5 Why We Use the IBIS Model 318
11.6 Data Used in Experiments 320
11.7 Experiment 1: Output Drive Capabity Versus Load 322
11.8 Experiment 2: Ccomp Loading 327
11.9 All-Important Zo: Algorithms and Field Solvers 332
11.10 Experiment 3: Edge Rate of a Driver and Reflections 333
11.11 Experiment 4: Using V-T Data Versus a Ramp 336
11.12 Experiment 5: Parasitics and Packaging Effects 346
11.13 Experiment 6: Environmental and Population Variables 349
11.14 Other Considerations: Timing and Noise Margin Issues 352
11.15 Experiment 7: Vol from Simulation Versus Data Sheet 356
11.16 How IBIS Handles Simulator Issues 358
11.17 Summary 359
12 Fixing Errors and Omissions in IBIS Models 361
12.1 IBIS Model Validation Steps 361
12.2 Process and Product Improvement Steps 362
12.3 Step 1: Detect and Acknowledge the Quality Problem 363
12.4 Step 2: Diagnose the Problem's Root Cause 364
12.5 Step 3: Design a Fix Based on Root Cause 366
12.6 Step 4: Verify the Fix 370
12.7 Step 5: Archive Corrected Models 372
12.8 Beyond Parsers and Checklists: Simulations and
Reality Checking 372
12.9 Tools Provided by the IBIS Committee 374
12.10 IBIS Common Errors Checklist and Correction Procedures.. 382
12.11 3Com's ISO 9000 Process for IBIS Models 386

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PART 5: MANAGING MODELS 425
14 Sources of IBIS Models 427
14.1 Model Needs Change as a Product is Developed 427
14.2 List of IBIS Model Sources 428
14.3 Using Default Models to Get Started 430
14.4 Using the Company's Model Library 430
14.5 Using the EDA Tool Provider's Model Library 430
14.6 Searching the Web for the SuppHer's Model 431
14.7 Requesting Models Directly from the Supplier 434
14.8 Purchasing a Commercial Third-Party Model Library 436
14.9 Using Models Adapted from Other Models 437
14.10 Review 440
14.11 Purchasing Custom Models from a Third-Party 441
14.12 Converting SPICE Models to IBIS Models 441
14.13 Using a Supplier's Preliminary Models 441
14.14 Asking SI-List and IBIS E-mail Reflectors for Help 450
14.15 Modeling Tools on the IBIS Website 451
14.16 Summary 452
15 Working with the Model Library 453
15.1 The Best Way to Manage Models 453
15.2 Component Standardization and Library Management 458
15.3 Storing and Retrieving Model Files 470
15.4 Assigning Models to Components in EDA Simulators 473
15.5 Flexibility in Model Choices at Run Time 476
15.6 Summary 476
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PART 6: MODEL ACCURACY AND VERIFICATION 477
16 Methodology for Verifying Models 479
16.1 Overview of Model Verification 479
16.2 Model Verification Methodology 481
16.3 Verifying SPICE Models 489
16.4 Verifying PDS Models 497
16.5 Verifying IBIS Models 503
16.6 Verifying Other Model Types 508
16.7 Summary 510
17 Verifying Model Accuracy by Using Laboratory Measurements .... 511
17.1 Introduction 511
17.2 Instrumentation Loading as a Source of Errors 512
17.3 Other Test Setup Errors 517
17.4 Signal Noise as a Source of Errors 519
17.5 Measurement Definitions and Terms as a Source of Errors... 520
17.6 Two Ways to Correlate Models with Measurements 522
17.7 Involving Production in Verification 523
17.8 An EMI/EMC Example 523
17.9 Correlating Unit-by-Unit Model Measurements 524
17.10 Statistical Envelope Correlation 525
17.11 Signal Integrity and Correlation 526
17.12 Waveform Correlation 527
17.13 Computational Electromagnetics and the Feature
Selective Validation Method 530
17.14 IBIS Golden Waveforms 534
17.15 How Unexpected Errors Led to an Advance in Modeling 535
17.16 Recommended Verification Strategy 541
17.17 Summary 544
18 Balancing Accuracy Against Practicality When Correlating
Simulation Results 545
18.1 Establishing Absolute Accuracy Is Difficult 545
18.2 Is a Model Accurate Enough to Be Usable? 547
18.3 Model Accuracy Definitions 547
18.4 Confidence Limits in Measurements and Simulations 548
18.5 How Much to Guard-Band Design Simulation? 549
18.6 Differences in Accuracy, Dispersion, and Precision for
Simulation and Measurement 550
18.7 Model Limitations 551
18.8 Standardization and the Compact Model Council 551
18.9 Summary 554
19 Deriving an Equation-Based Model from a Macromodel 555
19.1 A "New" RF Design Challenge 555
19.2 Background 555
19.3 Applying the RF Example to High-Speed Digital Circuits.... 556
19.4 Predicted and Measured Results 558
19.5 Reverse Isolation Analyzed 559
19.6 Optimizing Single-Stage Reverse Isolation 566
19.7 Combining Stages for Power Isolation 567
19.8 Calculations Versus Measurements 569
19.9 Construction and Test Techniques 569
19.10 Summary 570

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PART 7: FUTURE DIRECTIONS IN MODELING 571
20 The Challenge to IBIS 573
20.1 Emerging Simulation Requirements 573
20.2 The Leading Contenders to Change IBIS 576
20.3 Models in the Context of Simplification 577
20.4 Physical Modeling 578
20.5 Behavioral Modeling 580
20.6 Developing a Macromodel from the Behavioral Model 588
20.7 Developing a SPICE Macromodel from a Physical Model.... 592
20.8 Limitations in Models Due to Simplification 608
20.9 AMS Modeling Simplified 610
20.10 Limitations Because of Parameter Variation 618
20.11 Limitations of Deterministic Modeling and Design 621
20.12 Summary 629
21 Feedback to the Model Provider Improves Model Accuracy 631
21.1 Continuing Need for Better Models 631
21.2 How Far We Have Come 632
21.3 Four-Step Universal Process for Improvement 633
21.4 Specs That Swim Upstream; A New Approach 633
21.5 Warnings About Doing What-If Model Simulations 634
21.6 Selling the Idea of Better Models and Simulation 635
21.7 Summary 640
22 Future Trends in Modeling 641
22.1 Bridges to the Future 641
22.2 Challenge of HSDD 642
22.3 How Design Methods Have Changed 644
22.4 Attitudes in EMI/EMC about Modeling and Simulation 645
22.5 High-Speed Design Is Becoming More Challenging 646
22.6 Advantages of SPICE, S-Parameters, and IBIS 648
22.7 Combining Models and EDA Tools to Design
High-Speed Serial Busses 654
22.8 IBIS: Past, Present, and Future Specification Additions 655
22.9 Advantages of Pre-Layout Simulation for EMI/EMC 659
22.10 Interconnection Design Applied to EMI/EMC 660
22.11 Modeling for Power Integrity and EMI/EMC 661
22.12 Computational Electromagnetics 671
22.13 EDA Tool Supplier Survey 676
22.14 Risk Management and the Limitations of Simulation 681
22.15 Summary 681
23 Using Probability: The Ultimate Future of Simulation
Contributing author: Darren J. Carpenter, BTExact 683
23.1 Introduction 683
23.2 Limitations of Deterministic Modeling and Design 685
23.3 A New Approach: Probabilistic Modeling 687
23.4 Complexity of the EMI Chain of Cause and Effect 688
23.5 Risk Management Mathematics 689
23.6 Identical Equipments Case 692
23.7 Non-Identical Equipments Case 693
23.8 Risk Assessment 693
23.9 Distribution Examples 694
23.10 Review of Probability Distributions 701
23.11 Follow Up Simulation with Product Assurance 702
23.12 Summary 703
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PART 8: GLOSSARY, BIBLIOGRAPHY, INDEX, AND CD-ROM 705
Glossary 707
Bibliography 733
Index 745

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WIDE-BANDWIDTH HIGH DYNAMIC RANGE D/A CONVERTERS
- 218 Pages
- a Clear Version
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1 Digital to Analog conversion concepts 1
1.1 Functional aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Definition of the D/A function . . . . . . . . . . . . . . . . . . . 1
1.1.2 Functional specifications . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Algorithmic aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 Signal processing aspects . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.1 Waveforms and Line coding . . . . . . . . . . . . . . . . . . . . 11
1.3.2 Signal Modulation concepts . . . . . . . . . . . . . . . . . . . . 13
1.4 Circuit aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4.1 Architecture terminology . . . . . . . . . . . . . . . . . . . . . . 14
1.4.2 Resistive voltage division architectures . . . . . . . . . . . . . . 15
1.4.3 Capacitive voltage and charge division architectures . . . . . . . 16
1.4.4 Current division based architectures . . . . . . . . . . . . . . . . 18
1.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2 Framework for Analysis and Synthesis of DACs 19
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2 Framework description . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.1 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.2 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3 Current Steering DACs 25
3.1 Basic circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.1 Partitioning and segmentation . . . . . . . . . . . . . . . . . . . 26
3.1.2 Current switching network and current sources . . . . . . . . . . 29
3.1.3 Clock-data synchronization circuit . . . . . . . . . . . . . . . . . 29
3.1.4 Auxiliary circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2 Implementations and technology impact . . . . . . . . . . . . . . . . . . 30

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4 Dynamic limitations of Current Steering DACs 35
4.1 State of the art in dynamic linearity . . . . . . . . . . . . . . . . . . . . . 35
4.2 Dynamic limitations of current steering DACs . . . . . . . . . . . . . . . 40
4.2.1 Matching and relative amplitude precision . . . . . . . . . . . . . 41
4.2.2 Matching and relative timing precision . . . . . . . . . . . . . . 42
4.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5 Current Steering DAC circuit error analysis 45
5.1 Amplitude domain errors . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.1.1 Relative amplitude inaccuracies . . . . . . . . . . . . . . . . . . 45
5.1.2 Output resistance modulation . . . . . . . . . . . . . . . . . . . 47
5.2 Time domain errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.2.1 Nonlinear settling and output impedance modulation . . . . . . . 48
5.2.2 Asymmetrical switching . . . . . . . . . . . . . . . . . . . . . . 51
5.2.3 Modulation of switching behavior . . . . . . . . . . . . . . . . . 53
5.2.4 Charge feedthrough and injection . . . . . . . . . . . . . . . . . 54
5.2.5 Relative timing inaccuracies . . . . . . . . . . . . . . . . . . . . 56
5.2.6 Power supply bounce and substrate noise . . . . . . . . . . . . . 59
5.2.7 Clock (timing) jitter . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6 High-level modeling of Current Steering DACs 67
6.1 System modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.1.1 System layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.1.2 System excitations and responses . . . . . . . . . . . . . . . . . 69
6.1.3 System parameters . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.1.4 Subsystem interaction . . . . . . . . . . . . . . . . . . . . . . . 71
6.1.5 System modulation . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.2 Error properties and classification . . . . . . . . . . . . . . . . . . . . . 72
6.2.1 Error properties . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.2.2 Error classification . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3 Functional error generation mechanisms . . . . . . . . . . . . . . . . . . 79
6.3.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.2 Algorithmic modeling . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.3 Functional modeling . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.4 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

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7 Functional modeling of timing errors 89
7.1 Non-uniform timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.1.1 The Equivalent Timing error of a transition . . . . . . . . . . . . 89
7.1.2 Non-uniform timing in the process of signal sampling . . . . . . 91
7.1.3 Non-uniform timing in the process of signal creation . . . . . . . 92
7.2 Stochastic non-uniform timing analysis . . . . . . . . . . . . . . . . . . 95
7.2.1 Correlated non-uniform timing . . . . . . . . . . . . . . . . . . . 95
7.2.2 White non-uniform timing . . . . . . . . . . . . . . . . . . . . . 97
7.2.3 RZ and NRZ waveforms . . . . . . . . . . . . . . . . . . . . . . 100
7.3 Deterministic non-uniform timing . . . . . . . . . . . . . . . . . . . . . 103
7.3.1 Non-linear mapping of time domains . . . . . . . . . . . . . . . 103
7.3.2 Non-uniform timing in signal creation . . . . . . . . . . . . . . . 105
7.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
8 Functional analysis of local timing errors 109
8.1 Local timing error analysis . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.1.1 Equivalent timing error calculation . . . . . . . . . . . . . . . . . 109
8.1.2 Signal error calculation . . . . . . . . . . . . . . . . . . . . . . . 113
8.2 High level architectural parameter tradeoffs: segmentation . . . . . . . . 116
8.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9 Circuit analysis of local timing errors 119
9.1 Circuit analysis with linear models . . . . . . . . . . . . . . . . . . . . . 119
9.1.1 Circuit behavioral-level analysis of timing errors in a chain . . . . 120
9.1.2 Transistor level analysis . . . . . . . . . . . . . . . . . . . . . . 126
9.2 Local timing error tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.2.1 Switch timing errors . . . . . . . . . . . . . . . . . . . . . . . . 135
9.2.2 Latch timing errors . . . . . . . . . . . . . . . . . . . . . . . . . 137
9.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10 Synthesis concepts for CS DACs 139
10.1 Information management in the CS DAC . . . . . . . . . . . . . . . . . . 139
10.1.1 The basic current steering DAC hardware . . . . . . . . . . . . . 141
10.1.2 Information sources . . . . . . . . . . . . . . . . . . . . . . . . 141
10.1.3 Optional hardware: detection and control operations . . . . . . . 142
10.1.4 Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
10.1.5 Space/Time error mapping and processing . . . . . . . . . . . . . 145
10.2 Synthesis Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
10.3 A-posteriori error correction methods . . . . . . . . . . . . . . . . . . . 148
10.3.1 Calibration in amplitude and time domain . . . . . . . . . . . . . 148
10.3.2 Generalized mapping . . . . . . . . . . . . . . . . . . . . . . . . 151
10.3.3 Applications of generalized mapping . . . . . . . . . . . . . . . 155
10.3.4 Realization issues of the generalized mapping concept . . . . . . 156
10.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
11 Design of a 12 bit 500 Msample/s DAC 159
11.1 Design approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
11.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.2.1 Signaling and circuit logic . . . . . . . . . . . . . . . . . . . . . 160
11.2.2 Power supply and biasing . . . . . . . . . . . . . . . . . . . . . 161
11.2.3 Thermometer/binary bits partitioning . . . . . . . . . . . . . . . 162
11.3 Switched-Current cell .
11.3.1 Current source
11.3.2 Switch
11.4 Decoder, data synchronization and conditioning . . . . . . . . . . . . . . 174
11.4.1
11.4.2 Delay equalization . . .
11.4.3 Master-slave latches and drivers
11.4.4 Clock buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
11.5 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
11.6 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
11.6.1 DC linearity measurements . . . . . . . . . . . . . . . . . . . . . 180
11.6.2 AC linearity measurements . . . . . . . . . . . . . . . . . . . . . 181
11.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
References 185
A Output spectrum for timing errors 199
A.1 Power spectrum of y(t) for random timing errors . . . . . . . . . . . . . 199
A.2 Spectrum of y(t) for deterministic timing errors . . . . . . . . . . . . . . 202
B Literature data 203

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Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies
- 197 pages
- With 127 Figures
- clear contents

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HIGH-SPEED PHOTODIODES IN STANDARD CMOS TECHNOLOGY
- 157 pages
- Clear Contents
=========================================
1 Introduction 1
1.1 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Short range optical interconnection 7
2.1 Why optical interconnection? . . . . . . . . . . . . . . . . . . . . 7
2.1.1 Electrical and Optical Interconnection - Similarities . . . 8
2.1.2 Electrical and Optical Interconnection - Differences . . . . 9
2.2 Characteristics of light . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Optical fiber types . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.1 Single-mode fibers . . . . . . . . . . . . . . . . . . . . . . 12
2.3.2 Multimode fibers . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.3 Plastic optical fibers . . . . . . . . . . . . . . . . . . . . . 16
2.4 High intensity light sources . . . . . . . . . . . . . . . . . . . . . 16
2.4.1 Lasers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4.2 Light Emitting Diodes (LEDs) . . . . . . . . . . . . . . . 18
2.5 Photodetectors - introduction . . . . . . . . . . . . . . . . . . . . 18
2.5.1 Ideal photodetector . . . . . . . . . . . . . . . . . . . . . 19
2.5.2 Absorption of light in silicon . . . . . . . . . . . . . . . . 20
2.6 High-speed optical receivers in CMOS
for λ=850 nm-literature overview . . . . . . . . . . . . . . . . . 24
2.6.1 Using standard CMOS technology . . . . . . . . . . . . . 24
2.6.2 CMOS technology modification . . . . . . . . . . . . . . . 27
3 CMOS photodiodes for λ = 850 nm 33
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2 Bandwidth of photodiodes in CMOS . . . . . . . . . . . . . . . . 38
3.2.1 Intrinsic (physical) bandwidth . . . . . . . . . . . . . . . 38
3.2.2 Comparison between simulations and measurements . . . 61
3.2.3 N+/p-substrate diode . . . . . . . . . . . . . . . . . . . . 65
3.2.4 P+/nwell/p-substrate photodiode with low
-resistance substrate in adjoined-well technology . . . . . 66
3.3 Intrinsic (physical) photodiode bandwidth . . . . . . . . . . . . . 70
3.4 Extrinsic (electrical) photodiode bandwidth . . . . . . . . . . . . 72
3.5 Noise in photodiodes . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.6 Summary and conclusions . . . . . . . . . . . . . . . . . . . . . . 75

mscyc0909

4 High data-rates with CMOS photodiodes 79
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.2 Transimpedance amplifier design . . . . . . . . . . . . . . . . . . 81
4.2.1 Transimpedance amplifiers and extrinsic bandwidth . . . 82
4.2.2 Impact of noise: BER . . . . . . . . . . . . . . . . . . . . 83
4.2.3 Noise of the TIA . . . . . . . . . . . . . . . . . . . . . . . 84
4.3 Photodiode selection . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.4 Equalizer design . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.5 Robustness on spread and temperature . . . . . . . . . . . . . . . 91
4.6 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.6.1 Circuit details and measurement setup . . . . . . . . . . . 95
4.6.2 Optical receiver performance without equalizer . . . . . . 97
4.6.3 Optical receiver performance with equalizer . . . . . . . . 97
4.6.4 Robustness of the pre-amplifier: component spread . . . . 99
4.6.5 Robustness of the pre-amplifier: diode spread . . . . . . . 100
4.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5 Bulk CMOS photodiodes for λ = 400 nm 105
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.2 Finger nwell/p-substrate diode in adjoined-well technology. . . . 107
5.3 Finger n+/nwell/p-substrate diode . . . . . . . . . . . . . . . . . 109
5.3.1 Time domain measurements . . . . . . . . . . . . . . . . . 113
5.4 Finger n+/p-substrate photodiode in
separate-well technology . . . . . . . . . . . . . . . . . . . . . . . 115
5.5 Finger p+/nwell/p-substrate in
adjoined-well technology . . . . . . . . . . . . . . . . . . . . . . . 116
5.5.1 Time domain measurements . . . . . . . . . . . . . . . . . 117
5.6 p+/nwell photodiode . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6 Polysilicon photodiode 123
6.1 High-speed lateral polydiode . . . . . . . . . . . . . . . . . . . . 123
6.1.1 Pulse response of the poly photodiode . . . . . . . . . . . 127
6.1.2 Diffusion current outside the depletion region . . . . . . . 130
6.1.3 Frequency characterization of the
polysilicon photodiode . . . . . . . . . . . . . . . . . . . . 131
6.2 Noise in polysilicon photodiodes . . . . . . . . . . . . . . . . . . 134
6.2.1 Dark leakage current in the polysilicon diode . . . . . . . 134
6.3 Time domain measurements . . . . . . . . . . . . . . . . . . . . . 135
6.4 Quantum efficiency and sensitivity . . . . . . . . . . . . . . . . . 138
6.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139