(11月30日增加12本)★好书大放送——Springer丛书系列★EE，CS & DSP★

mscyc0909

Digital Phase Lock Loops -- Architectures and Applications
==================================================
Contents
Preface xi
Acknowledgement xv
Acronyms xvii
1 General Review of Phase-Locked Loops 1
1.1 Overview of Phase-Locked Synchronization Schemes . . . . . . . 1
1.2 The Synchronization Challenge . . . . . . . . . . . . . . . . . . 3
1.3 Phase-Locked Loops . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3.1 Analog Phase-locked Loops . . . . . . . . . . . . . . . . 4
1.3.2 PLL Basic Components . . . . . . . . . . . . . . . . . . 6
1.3.3 PLL analysis . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 Digital Phase Lock Loops 15
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Classification of DPLLs . . . . . . . . . . . . . . . . . . . . . . . 16
2.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3 The Time-Delay Digital Tanlock Loops (TDTLs) 31
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2 Structure and SystemEquation . . . . . . . . . . . . . . . . . . 32
3.2.1 Structure of the TDTL . . . . . . . . . . . . . . . . . . . 32
3.2.2 SystemEquation . . . . . . . . . . . . . . . . . . . . . . 32
3.2.3 The Characteristic Function . . . . . . . . . . . . . . . . 34
3.3 SystemAnalysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.3.1 First-order TDTL . . . . . . . . . . . . . . . . . . . . . . 35
3.3.2 Second-Order TDTL . . . . . . . . . . . . . . . . . . . . 43
3.4 Locking Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.4.1 Convergence of the First-Order TDTL . . . . . . . . . . 46
3.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4 Hilbert Transformer and Time-Delay 51
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2 Statistical Behavior of HT and Time-Delay in i.i.d. Additive
Gaussian Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.2.1 Input-Output Relationships in the Presence of Noise . . 53
4.2.2 Joint PDF of the Amplitude and Phase Random Variables 54
4.2.3 PDF of the Phase Random Variable . . . . . . . . . . . . 56
4.2.4 PDF of the Phase Noise . . . . . . . . . . . . . . . . . . 57
4.2.5 Expectation and Variance of the Phase Noise . . . . . . 58
4.2.6 The phase Estimator and Ranges of Cramer-Rao Bounds 62
4.2.7 A Symmetric Transformation . . . . . . . . . . . . . . . 65
4.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5 The Time-delay Digital Tanlock Loop in Noise 69
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.2 Noise Analysis of the TDTL . . . . . . . . . . . . . . . . . . . . 70
5.2.1 SystemEquation . . . . . . . . . . . . . . . . . . . . . . 70
5.2.2 Statistical Behavior of TDTL Phase Error Detector . . . 71
5.2.3 Phase Estimation and Cramer-Rao Bounds . . . . . . . . 74
5.2.4 Statistical Behavior of the TDTL in Gaussian Noise . . . 77
5.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6 Architectures for Improved Performance 85
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.2 Simulation Results of First-Order TDTL . . . . . . . . . . . . . 85
6.3 Improved First-Order TDTL Architectures . . . . . . . . . . . . 88
6.3.1 Delay Switching Architecture . . . . . . . . . . . . . . . 89
6.3.2 Adaptive Gain Architecture . . . . . . . . . . . . . . . . 94
6.3.3 Combined Delay Switching and Adaptive Gain . . . . . . 100
6.3.4 Sample Sensing Adaptive Architecture . . . . . . . . . . 105
6.3.5 Early Error Sensing Adaptive Architecture . . . . . . . . 113
6.4 Simulation Results of Second-Order TDTL . . . . . . . . . . . . 115
6.5 Improved Second-Order TDTL Architectures . . . . . . . . . . . 121
6.5.1 Adaptive Filter Coefficients Second-Order TDTL . . . . 121
6.5.2 Adaptive Loop Gain Second-Order TDTL . . . . . . . . 123
6.6 A Variable Order TDTL Architecture . . . . . . . . . . . . . . . 123
6.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7 FPGA Reconfigurable TDTL 137
7.1 Overview of Reconfigurable Systems . . . . . . . . . . . . . . . . 137
7.2 FPGA Structure and Operation . . . . . . . . . . . . . . . . . . 138
7.3 Xtreme DSP Development System. . . . . . . . . . . . . . . . . 142
7.4 TDTL FPGA Implementation . . . . . . . . . . . . . . . . . . . 149
7.4.1 The CORDIC Arctangent Block . . . . . . . . . . . . . . 151
7.4.2 The Digital Controlled Oscillator . . . . . . . . . . . . . 152
7.4.3 The CORDIC Divider . . . . . . . . . . . . . . . . . . . 154
7.5 Real-Time TDTL Results . . . . . . . . . . . . . . . . . . . . . 156
7.5.1 First-Order TDTL . . . . . . . . . . . . . . . . . . . . . 157
7.5.2 Second-Order TDTL . . . . . . . . . . . . . . . . . . . . 157
7.5.3 Sample Sensing Adaptive TDTL . . . . . . . . . . . . . . 159
7.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
8 Selected Applications 165
8.1 PM Demodulation Using TDTL . . . . . . . . . . . . . . . . . . 165
8.2 Performance in Gaussian Noise . . . . . . . . . . . . . . . . . . 169
8.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . 171
8.4 FSK and FMDemodulation . . . . . . . . . . . . . . . . . . . . 172
8.5 Wideband FMSignal Detection . . . . . . . . . . . . . . . . . . 173
8.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Bibliography 179
Index 189

mscyc0909

"Circuits and Systems Based on Delta Modulation - Linear, Nonlinear,and Mixed Mode Processing"
- With 130 Figures
- 208 pages
- a clear version

mscyc0909

ΣΔ A/D CONVERSION FOR SIGNAL CONDITIONING
=========================================
Contents
List of symbols and abbreviations ix
1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 The signal conditioning channel 9
2.1 Generic communication channel . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Performance parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Conventional conditioning channels . . . . . . . . . . . . . . . . . . . . 10
2.4 Evolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.1 Technology advances . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4.2 System demands . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.3 Advances in digital signal processing and analog circuit design . . 14
2.4.4 Digitization of the architecture . . . . . . . . . . . . . . . . . . . 14
2.5 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3
 A/D conversion 21
3.1 Historical overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 State-of-the-art in
 A/D conversion . . . . . . . . . . . . . . . . . . . 22
3.2.1 Architectural considerations . . . . . . . . . . . . . . . . . . . . 23
3.2.2 Implementation aspects . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.3 Performance metrics for
 ADCs . . . . . . . . . . . . . . . . 28
3.3
 ADCs in future conditioning channels . . . . . . . . . . . . . . . . . 29
3.3.1 The Shannon theorem and
 based signal conditioning . . . . . 29
3.3.2 Comparison of Nyquist and
 based signal conditioning . . . . 30
3.3.3 Survey of published power/performance values . . . . . . . . . . 32
3.4 Limitations of
 A/D conversion . . . . . . . . . . . . . . . . . . . . . 32
3.4.1 Linear limitations . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.4.2 Non-linear limitations . . . . . . . . . . . . . . . . . . . . . . . 33
3.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4 Power consumption in channel building blocks 37
4.1 Literature on power/performance analysis . . . . . . . . . . . . . . . . . 37
4.2 Figures-of-merit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.2.1 FOM related to thermal noise . . . . . . . . . . . . . . . . . . . 38
4.2.2 FOM including distortion . . . . . . . . . . . . . . . . . . . . . 39
4.2.3 FOM related to signal resolution . . . . . . . . . . . . . . . . . . 39
4.3 Power consumption in analog conditioning circuits . . . . . . . . . . . . 41
4.3.1 Power/performance relations . . . . . . . . . . . . . . . . . . . . 41
4.3.2 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.4 Power consumption in a
ADC . . . . . . . . . . . . . . . . . . . . . 44
4.4.1 Power/performance relations . . . . . . . . . . . . . . . . . . . . 44
4.4.2 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.5 Power consumption in digital conditioning circuits . . . . . . . . . . . . 47
4.5.1 Filter functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.5.2 Power/performance relations . . . . . . . . . . . . . . . . . . . . 50
4.5.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.6 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5 Full-analog and full-digital conditioning channels 57
5.1 Full-analog conditioning channel . . . . . . . . . . . . . . . . . . . . . . 57
5.1.1 The conditioning channel . . . . . . . . . . . . . . . . . . . . . . 58
5.2 Full-digital conditioning channel . . . . . . . . . . . . . . . . . . . . . . 59
5.2.1 The conditioning channel . . . . . . . . . . . . . . . . . . . . . . 59
5.2.2 Power/performance analysis . . . . . . . . . . . . . . . . . . . . 61
5.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

mscyc0909

6 Conditioning
 ADCs 67
6.1 Generic conditioning
ADC . . . . . . . . . . . . . . . . . . . . . . . 67
6.1.1 Concept of operation . . . . . . . . . . . . . . . . . . . . . . . . 67
6.1.2 Universal model of a
 modulator . . . . . . . . . . . . . . . . 72
6.1.3 Interferer immunity . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.1.4 Power/performance analysis . . . . . . . . . . . . . . . . . . . . 77
6.2 Signal conditioning in the decimation filter . . . . . . . . . . . . . . . . . 79
6.2.1 Interferer immunity . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.2.2 The conditioning channel . . . . . . . . . . . . . . . . . . . . . . 81
6.2.3 Power/performance analysis . . . . . . . . . . . . . . . . . . . . 82
6.3 Signal conditioning with a restricted filtering STF . . . . . . . . . . . . . 84
6.3.1 Interferer immunity . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.2 The conditioning channel . . . . . . . . . . . . . . . . . . . . . . 87
6.3.3 Power/performance analysis . . . . . . . . . . . . . . . . . . . . 89
6.3.4 Conditioning hybrid
ADC . . . . . . . . . . . . . . . . . . . 92
6.4 Signal conditioning by unrestricted STF design . . . . . . . . . . . . . . 94
6.4.1 Interferer immunity . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.4.2 The conditioning channel . . . . . . . . . . . . . . . . . . . . . . 98
6.4.3 Power/performance analysis . . . . . . . . . . . . . . . . . . . . 98
6.5 Comparison of conditioning ADCs . . . . . . . . . . . . . . . . . . . . . 99
6.5.1 Comparison of topologies . . . . . . . . . . . . . . . . . . . . . 100
6.5.2 Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.5.3 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.5.4 Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7 Digitization of the inter-die interface 105
7.1 Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7.2 Power in the interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.2.1 Analog interface . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.2.2 Digital interface after decimation . . . . . . . . . . . . . . . . . 108
7.2.3 Digital interface before decimation . . . . . . . . . . . . . . . . 108
7.2.4 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.3 Application to the conditioning channels . . . . . . . . . . . . . . . . . . 110
7.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
8 Highly analog and highly digital channels for FM/AM radio 113
8.1 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8.1.1 Conventional radio with analog demodulation . . . . . . . . . . . 114
8.1.2 Radio with digital demodulation . . . . . . . . . . . . . . . . . . 115
8.2 VGA design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
8.2.1 Highly linear VGA design . . . . . . . . . . . . . . . . . . . . . 117
8.2.2 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
8.3 ADC design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
8.3.1 Conventional solutions . . . . . . . . . . . . . . . . . . . . . . . 124
8.3.2
 ADC with integrated passive mixer . . . . . . . . . . . . . . 125
8.3.3 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
8.4 Evaluation of the channel . . . . . . . . . . . . . . . . . . . . . . . . . . 135
8.4.1 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
8.4.2 Benchmark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
8.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
9 Conditioning
 ADCs for Bluetooth 139
9.1 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
9.1.1 Conventional radio with analog demodulation . . . . . . . . . . . 140
9.1.2 Radio with digital demodulation and analog signal-conditioning . 141
9.1.3 Radio with digital demodulation, without analog signal conditioning141
9.2 Feed forward
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
9.2.1 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
9.2.2 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
9.3 Conditioning feedback
ADC . . . . . . . . . . . . . . . . . . . . . . 156
9.3.1 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
9.3.2 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
9.4 FFB-ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
9.4.1 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
9.4.2 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
9.5 Evaluation of the channels . . . . . . . . . . . . . . . . . . . . . . . . . 181
9.5.1 Benchmark with published ADCs . . . . . . . . . . . . . . . . . 182
9.5.2 Comparison of the presented ADCs . . . . . . . . . . . . . . . . 182
9.5.3 Benchmark with published Bluetooth conditioning channels . . . 187
9.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
10 General conclusions 191
A Overview of published
 ADCs 193
B Power/performance relation of analog circuits 199
B.1 Simple differential pair . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
B.2 Differential pair in a global feed-back configuration . . . . . . . . . . . . 200
B.3 Degenerated differential pair . . . . . . . . . . . . . . . . . . . . . . . . 201
C Power/performance relation of digital filters 203
C.1 Analysis of the filter topology . . . . . . . . . . . . . . . . . . . . . . . 203
C.2 Calculation of filter parameters . . . . . . . . . . . . . . . . . . . . . . . 204
C.3 Calculation of power consumption . . . . . . . . . . . . . . . . . . . . . 205
C.4 Extension to other implementations . . . . . . . . . . . . . . . . . . . . 206
D Third-order distortion in analog circuits and
 ADCs 207
E Power consumption in a data interface 211
E.1 Analog data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
E.2 Digital data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
References 215

mscyc0909

DESIGN OF VERY HIGH-FREQUENCY MULTIRATE SWITCHEDCAPACITOR CIRCUITS
-- Extending the Boundaries of CMOS Analog Front-End Filtering

1 INTRODUCTION 1
1. High-Frequency Integrated Analog Filtering...................................1
2. Multirate Switched-Capacitor Circuit Techniques...........................3
3. Sampled-Data Interpolation Techniques..........................................5
4. Research Goals and Design Challenges...........................................8
2 IMPROVEDMULTIRATE POLYPHASE-BASED INTERPOLATION
STRUCTURES 15
1. Introduction....................................................................................15
2. Conventional and Improved Analog Interpolation.........................16
3. Polyphase Structures for Optimum-class Improved Analog
Interpolation ...................................................................................20
4. Multirate ADB Polyphase Structures.............................................22
4.1 Canonic and Non-Canonic ADB Realizations .......................22
4.1.1 FIR System Response .................................................22
4.1.2 IIR System Response ..................................................24
4.2 SC Circuit Architectures ........................................................26
5. Low-Sensitivity Multirate IIR Structures.......................................33
5.1 Mixed Cascade/Parallel Form ...............................................33
5.2 Extra-Ripple IIR Form ...........................................................37
6. Summary ........................................................................................37
3 PRACTICAL MULTIRATE SC CIRCUIT DESIGN CONSIDERATIONS 41
1. Introduction....................................................................................41
2. Power Consumption Analysis ........................................................41
3. Capacitor-Ratio Sensitivity Analysis .............................................44
3.1 FIR Structure ........................................................................44
3.2 IIR Structure ........................................................................46
4. Finite Gain & Bandwidth Effects...................................................49
5. Input-Referred Offset Effects.........................................................49
6. Phase Timing-Mismatch Effects ....................................................55
6.1 Periodic Fixed Timing-Skew Effect........................................55
6.2 Random Timing-Jitter Effects.................................................59
7. Noise Analysis ...............................................................................59
8. Summary ........................................................................................65

mscyc0909

4 GAIN- AND OFFSET- COMPENSATION FOR MULTIRATE SC
CIRCUITS 69
1. Introduction....................................................................................69
2. Autozeroing and Correlated-Double Sampling Techniques ..........70
3. AZ and CDS SC Delay Blocks with Mismatch-Free Property ......72
3.1 SC Delay Block Architectures ................................................72
3.2 Gain and Offset Errors – Expressions and Simulation
Verification .....................................................................77
3.3 Multi-Unit Delay Implementations.........................................80
4. AZ and CDS SC Accumulators......................................................82
4.1 SC Accumulator Architectures ...............................................82
4.2 Gain and Offset Errors – Expressions and Simulation
Verificatio n ........................................................................82
5. Design Examples............................................................................84
6. Speed and Power Considerations ...................................................89
7. Summary ........................................................................................94

5 DESIGN OF A 108MHZMULTISTAGE SC VIDEO INTERPOLATING
FILTER 99
1. Introduction....................................................................................99
2. Optimum Architecture Design .....................................................101
2.1 Multistage Polyphase Structure with Half-Band Filtering ..101
2.2 Spread-Reduction Scheme....................................................102
2.3 Coefficient-Sharing Techniques ...........................................103
3. Circuit Design ..............................................................................106
3.1 1st-Stage ...................................................................106
3.2 2nd- and 3rd-Stage .................................................................109
3.3 Digital Clock Phase Generation ..........................................111
4. Circuit Layout ..............................................................................113
5. Simulation Results .......................................................................114
5.1 Behavioral Simulations ........................................................114
5.2 Circuit-Level Simulations.....................................................115
6. Summary ......................................................................................118

6 DESIGN OF A 320MHZ FREQUENCY-TRANSLATED SC BANDPASS
INTERPOLATING FILTER 123
1. Introduction..................................................................................123
2. Prototype System-Level Design...................................................125
2.1 Multi-notch FIR Transfer Function......................................125
2.2 Time-Interleaved Serial ADB Polyphase Structure with
Autozeroing ...................................................................127
3. Prototype Circuit-Level Design ...................................................128
3.1 Autozeroing ADB and Accumulator.....................................128
3.2 High-Speed Multiplexer .......................................................130
3.3 Overall SC Circuit Architecture...........................................133
3.4 Telescopic opamp with Wide-Swing Biasing........................133
3.5 nMOS Switches 136
3.6 Noise Calculation.................................................................137
3.7 I/O Circuitry ...................................................................138
3.8 Low Timing-Skew Clock Generation....................................138
4. Layout Considerations .................................................................143
4.1 Device and Path Matching...................................................143
4.2 Substrate and Supply Noise Decoupling ..............................147
4.3 Shielding ...................................................................151
4.4 Floor Plan ...................................................................151
5. Simulation Results .......................................................................152
5.1 Opamp Simulations ..............................................................152
5.2 Filter Behavioral Simulations ..............................................155
5.3 Filter Transistor-Level and Post-Layout Simulations.............156
6. Summary ......................................................................................158

mscyc0909

7 EXPERIMENTAL RESULTS 163
1. Introduction..................................................................................163
2. PCB Design..................................................................................163
2.1 Floor Plan ...................................................................164
2.2 Power Supplies and Decoupling ..........................................167
2.3 Biasing Currents ..................................................................167
2.4 Input and Output Network....................................................167
3. Measurement Setup and Results ..................................................169
3.1 Frequency Response.............................................................170
3.2 Time-Domain Signal Waveforms .........................................172
3.3 One-Tone Signal Spectrum...................................................172
3.4 Two-Tone Intermodulation Distortion .................................174
3.5 THD and IM3 vs. Input Signal Level....................................177
3.6 Noise Performance...............................................................177
3.7 CMRR and PSRR..................................................................180
4. Summary ......................................................................................181
8 CONCLUSIONS 187
APPENDIX 1 TIMING-MISMATCH ERRORS WITH
NONUNIFORMLY HOLDING EFFECTS....................191
1. Spectrum Expressions for IU-ON(SH) and IN-CON(SH)...........193
1.1 IU-ON(SH) ...................................................................193
1.2 IN-CON(SH) ...................................................................197
2. Closed Form SINAD Expression for IU-ON(SH) and INCON(
SH) .....................................................................................197
2.1 IU-ON(SH) ...................................................................198
2.2 IN-CON(SH) ...................................................................201
3. Closed Form SFDR Expression for IN-CON(SH) systems .........203
4. Spectrum Correlation of IN-OU(IS) and IU-ON(SH)..................205
APPENDIX 2 NOISE ANALYSIS FOR SC ADB DELAY LINE
AND POLYPHASE SUBFILTERS .................................215
1. Output Noise of ADB Delay Line................................................215
2. Output Noise of Polyphase Subfilters ..........................................217
2.1 Using TSI Input Coefficient SC Branches ............................217
2.2 Using OFR Input Coefficient SC Branches..........................220
APPENDIX 3 GAIN, PHASE AND OFFSET ERRORS FOR GOC
MF SC DELAY CIRCUIT I AND J ................................221
1. GOC MF SC Delay Circuit I........................................................221
2. GOC MF SC Delay Circuit J........................................................225

mscyc0909

LNA-ESD CO-DESIGN FOR FULLY INTEGRATED CMOS WIRELESS RECEIVERS
========================================================
Contents
Abstract
List of Symbols and Abbreviations
1 Introduction 1
1.1 The Growth of the Wireless Communication Market . . . . . . . . . . . . . . . . 1
1.2 Evolution to CMOS RF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 CMOS, RF and ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Outline of this Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Low-Noise Amplifiers in CMOS Wireless Receivers 9
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Some Important RF Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.1 Quality Factor of Reactive Elements and Series-Parallel Transformation . 9
2.2.2 SNR and Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.3 Impedance Matching, Power Matching, Noise Matching . . . . . . . . . 12
2.2.4 Transducer Power Gain, Operating Power Gain and Available Power Gain 13
2.2.5 Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 The Deep Sub-Micron MOS Transistor at Radio Frequencies . . . . . . . . . . . 17
2.3.1 MOS Model for Hand Calculations . . . . . . . . . . . . . . . . . . . . 17
2.3.2 Linearity of the short-channel MOS transistor . . . . . . . . . . . . . . . 18
2.3.3 Non-Quasi Static Model . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.4 Extended MOS Model for Simulation . . . . . . . . . . . . . . . . . . . 21
2.4 The Origin of Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.1 Resistor Thermal Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.2 Thermal Noise in MOS transistors . . . . . . . . . . . . . . . . . . . . . 22
2.4.2.1 Classical MOS Channel Noise . . . . . . . . . . . . . . . . . 22
2.4.2.2 Induced Gate Noise . . . . . . . . . . . . . . . . . . . . . . . 23
2.4.3 1/f Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4.4 Shot Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.5 The LNA in the Receiver Chain . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5.1 Cascading Non-Ideal Building Blocks . . . . . . . . . . . . . . . . . . . 25
2.5.1.1 Noise in a Cascade . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5.1.2 IIV3 of a Cascade . . . . . . . . . . . . . . . . . . . . . . . . 26
2.5.2 Wireless Receiver Architectures . . . . . . . . . . . . . . . . . . . . . . 27
2.5.3 LNA Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.5.3.1 Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.5.3.2 Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.5.3.3 Voltage Gain or Power Gain . . . . . . . . . . . . . . . . . . . 29
2.5.3.4 Intermodulation Distortion . . . . . . . . . . . . . . . . . . . 31
2.5.3.5 Reverse Isolation . . . . . . . . . . . . . . . . . . . . . . . . 31
2.5.3.6 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.5.3.7 Single-ended vs. Differential . . . . . . . . . . . . . . . . . . 32
2.6 Topologies for Low-Noise Amplifiers . . . . . . . . . . . . . . . . . . . . . . . 33
2.6.1 The Inductively Degenerated Common Source LNA . . . . . . . . . . . 33
2.6.1.1 From Basic Common-Source Amplifier to Inductively Degenerated
Common-Source LNA . . . . . . . . . . . . . . . . . . 33
2.6.1.2 Power Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.6.1.3 Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.6.1.4 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.6.2 The Common-Gate LNA . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.6.2.1 Input Matching . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.6.2.2 Power Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.6.2.3 Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.6.2.4 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.6.3 Shunt-Feedback Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.6.4 Image Reject LNA’s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.6.5 Highly Linear Feedforward LNA . . . . . . . . . . . . . . . . . . . . . 51
2.6.6 The Noise-Cancelling Wide-band LNA . . . . . . . . . . . . . . . . . . 52
2.6.7 Current Reuse LNA with Interstage Resonance . . . . . . . . . . . . . . 52
2.6.8 Transformer Feedback LNA . . . . . . . . . . . . . . . . . . . . . . . . 53
2.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

mscyc0909

3 ESD Protection in CMOS 55
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.2 ESD Tests and Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.2.1 Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.2.2 Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.2.3 Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.2.4 Transmission Line Pulsing . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.3 ESD-Protection in CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.3.1 ESD-Protection Devices . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.3.1.1 Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.3.1.2 Grounded-Gate NMOS . . . . . . . . . . . . . . . . . . . . . 63
3.3.1.3 Gate-Coupled NMOS . . . . . . . . . . . . . . . . . . . . . . 66
3.3.1.4 Silicon-Controlled Rectifier . . . . . . . . . . . . . . . . . . . 66
3.3.2 ESD-Protection Topologies . . . . . . . . . . . . . . . . . . . . . . . . 68
3.3.2.1 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.3.2.2 Power Supply Clamping . . . . . . . . . . . . . . . . . . . . . 69
3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4 Detailed Study of the Common-Source LNA with Inductive Degeneration 73
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.2 The Non-Quasi Static Gate Resistance . . . . . . . . . . . . . . . . . . . . . . . 73
4.2.1 Influence of rg,NQS on Zin, GT and IIP3 . . . . . . . . . . . . . . . . . . 74
4.2.2 Influence of rg,NQS on the Noise Figure . . . . . . . . . . . . . . . . . . 75
4.3 Parasitic Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.3.1 Impact of Cp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.3.1.1 Influence of Cp on Input Matching . . . . . . . . . . . . . . . 80
4.3.1.2 Influence of Cp on Power Gain, Noise Figure and IIP3 . . . . . 82
4.3.2 Impact of Cp Non-Linearity . . . . . . . . . . . . . . . . . . . . . . . . 85
4.3.3 Impact of the Finite Q of Cp . . . . . . . . . . . . . . . . . . . . . . . . 88
4.4 Miller Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.5 Optimization of the Cascode Transistor . . . . . . . . . . . . . . . . . . . . . . 91
4.6 Output Capacitance Non-Linearity . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.7 Impact of a Non-Zero S11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.8 Output Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.8.1 Load Impedance Constraints . . . . . . . . . . . . . . . . . . . . . . . . 96
4.8.2 Output Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.9 LNA Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.10 Layout Aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.10.1 RF Bonding Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.10.2 On-Chip Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.10.2.1 Modelling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.10.2.2 Patterned Ground Shields . . . . . . . . . . . . . . . . . . . . 103
4.10.3 The Amplifying Transistor . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.10.4 The Cascode Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.11 The Common-Gate LNA Revisited . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.12 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

mscyc0909

5 RF-ESD Co-Design for CMOS LNA’s 111
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.2 ESD-protection within an L-Type Matching Network . . . . . . . . . . . . . . . 112
5.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.2.2 General Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.2.3 Design and Layout of the ESD Protection Diodes . . . . . . . . . . . . . 115
5.2.4 Non-Linearity of Input ESD Protection Diodes . . . . . . . . . . . . . . 116
5.2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.3 ESD-Protection within a Π-Type Matching Network . . . . . . . . . . . . . . . . 119
5.4 Inductive ESD-Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.5 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.6 Other ESD-Protection Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.6.1 Distributed ESD-Protection . . . . . . . . . . . . . . . . . . . . . . . . 128
5.6.2 ESD-Protection with T-Coils . . . . . . . . . . . . . . . . . . . . . . . . 130
5.7 ESD-Protection for the Common-GateLNA . . . . . . . . . . . . . . . . . . . . 130
5.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6 Integrated CMOS Low-Noise Amplifiers 133
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.2 A 0.8 dB NF ESD-Protected 9 mW CMOS LNA . . . . . . . . . . . . . . . . . 133
6.2.1 The GPS Power Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.2.2 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.2.3 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.2.4 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.2.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.2.6 Discussion and Comparison . . . . . . . . . . . . . . . . . . . . . . . . 144
6.2.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.3 A 1.3 dB NF CMOS LNA for GPS with 3 kV HBM ESD-Protection . . . . . . . 147
6.3.1 The Complete GPS Receiver Front-End . . . . . . . . . . . . . . . . . . 147
6.3.1.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.3.1.2 Low-Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . 148
6.3.1.3 Quadrature, Direct Digital Downconversion . . . . . . . . . . 148
6.3.1.4 PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . 149
6.3.2 The Low Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.3.3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.4 A 5 GHz LNA with Inductive ESD-Protection Exceeding 3 kV HBM . . . . . . . 159
6.4.1 5 GHz Wireless LAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.4.2 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
6.4.3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
6.4.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
7 Conclusions 171
A Fundamentals of Two-Port Noise Theory 173
Index 175