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[招聘] 内部推荐 后端 ,DFT ,上海浦东

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发表于 2019-7-31 17:44:41 | 显示全部楼层 |阅读模式

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本帖最后由 大龄文艺男青年 于 2019-8-1 19:50 编辑




#1 DFT  Engineer
Requirements:
1、Bachelor degree or above,major in Electronic and Information Engineering.
2、Above five years working experience in relavant industry.
3、Good communication and positive.

Responsibility:
As a member of DFT engineering team, the candidate will develop methodologies and implement DFT forpre/post-silicon DFT flow.
- Work with digital design team and PD to meet low cost and high quality testing.
-Define DFT plan and execute DFT/ATPG tasks.
- Block level and top level DFT implementation.
- Co-work with RTL design to implement DFT circuit.
- DFT architecture enhancement.
- ATPG pattern simulation.
-Knowledge of synthesis , STA .

############################################################

#2 Physical Design Engineer

Responsibility:
1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing.
2. Experience in  STA timing analysis and fixing.
3. Perform physical verification, including DRC, LVS, IR drop and EM analysis.

Requirements:
1. Familiar with Cadence innovus or Synopsys ICC2.

2.  Have experiences under 14nm IC design experiences will be plus.


Eamil resume to:szl_hi@126.com




发表于 2019-8-1 12:28:41 | 显示全部楼层
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不是猎头,已帮您推荐  发表于 2019-8-1 13:03
发表于 2019-8-3 17:06:16 | 显示全部楼层
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