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【上海/北京】Cadence紧急招聘职位列表，内推，加速应聘流程
有兴趣的朋友可以把简历发到我邮箱，并注明你想投递的职位，我会和用人部门老大直接电话沟通，无论结果如何都会给予答复
mariojiang@hotmail.com
1.
Position: Lead Product Validation Engineer
Job Description SigrityShanghai Product Validation team is looking for an engineer with experience insignal integrity/power integrity analysis and product verification. You will beresponsible for testing and overseeing the quality management of Sigrityproducts, the industry leading SI/PI analysis products. You will be involved inworld latest SI/PI analysis technologies development to help our customerscreate most innovative products. Duties:
- Work within a global multi-functional team to review SI/PI analysis technologies, project plans and functional specifications, develop test criteria and write test plans, manually exercise and test functionality of the Sigrity products
- Develop automated tests within the existing test environment
- Maintain comprehensive regression suites for monitoring products quality
- Work with the team to solve customer issues
Requirements:
- BS degree or MS degree with 2+ years SI/PI related experience
- Understand test processes and methodologies in a software development environment
- Good understanding of power integrity and signal integrity
- Be familiar with Linux system, and scripting skills with TCL or Perl or Shell is a plus
- Knowledge of PCB design, routing, and packaging is a plus
- Having good analytical and problem solving skills is essential
- Strong written and verbal communication skills, in English and Chinese are mandatory
- Self-starter, self-sufficient, able to work independently as well as with teams, able to multitask
2.
Principal Design Engineer (数字前端设计)
Position Description:
Deliver/implement DDR IP. The engineer should be able to act as a strong team member and contributor, leading team projects and initiatives. Exercise judgment within generally defined practices and policies.
Specific duties include:
- Be responsible for building and leading a high-performance IC design team, owning the IC micro-architecture, package and test platform development, refining the EDA design flow
- Proficiency in logic design, simulation, synthesis, STA and testing
- Proficiency in Verilog and its simulation environment
- Good knowledge of IC design
* At least five years experience driving complex IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.
Position Requirements:
1. Essential Qualifications: Must have BS degree with 6+ years of applicable experience, MS degree with 4+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
2. Essential that the individual demonstrates strong communication, verbal and written.
3. Requires good communication skills in English.
Lead design engineer-STA
Position Description:
1. In charge of DDR IP logic design Implementation.
2. Daily duties include: RTL coding(plus), Logic Synthesis(must), Static Timing Analysis(must).
3. HDL language Knowledge, like verilog or vhdl is necessary.
4. C/C++/perl/tcl/csh/python, UNIX, Linux experience are plus.
5. Excellent analytical and problem-solving skills. Quick learner-able to learn and apply technical and complex topics.
6. Excellent communication skills and the uncanny ability in a cooperative team environment are required.
7. Self-motivated, result-oriented, can take ownership and follow-through on tasks.
Position Requirements:
Essential Qualifications:
1. Master degree with 4~7 years’ experience
2. Major in Micro-electronics, Electronic Engineering, Computer Science, Information Technology or equivalent
3. Ability to work effectively alone or as well as in the team.
4. Essential that the individual demonstrates strong communication, verbal and written
5. Requires good communication skills in English.
Desirable Qualifications:
1. Experience of DDR
3. 其他紧急职位列表
DSG | | Principal Product Engineer | | Product Validation Engineer I | | IPG | | Principal Product Engineer - PHY IP | | Lead Design Engineer-Synthesis | | Principle Design Engineer - IC Front End | | SVG | | | | | | Field Service Engineer II | | WFO | | Principal / Lead Application Engineer (Physical Design) | | Senior Account Technical Executive I - Verification | | Leader Application Engineer
(Digital Signoff: Tempus/Genus) | | Principal Application Engineer
(Digital Backend) |
|
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发表于 2019-7-24 08:54:59
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