概念请教scenic routing 是什么意思？为啥设置要设置set_max_delay,不用set_false_path

watertree

Earlier, the methodology was to set false paths between the clock domains. This can cause re-convergence
issues if two functionally-related signals are crossing from one domain to another domain. In a highly
congested ASIC, the backend tools could do scenic routing if there are no constraints on the clock-crossing
signals (false path) causing functional failures.
The following synthesis methodology is required for achieving successful functional operation of the
controller:
1.  Do not set false path between the clock domains. Setting false paths between the clock domains cause
scenic routing.
Example: set_false_path -from bus_clk -to mac_clk. This is not recommended.
2.  Set max_delay constraint between the clock domains. This avoids scenic routing. The max_delay
should match the maximum allowed skew between two related signals by design and also the
maximum delays used in the re-convergence simulation.