Cadence 2019年 校招、社招急招多岗位 内推名额

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A.Title: Principal Product Engineer
Location: SH

Position Description:
1. The Product Engineering team works with Customers and foundries, R&D, Marketing, and the Field Applications Engineers to create products that address the unique and complex needs of our customers.
2. A Physical Verification Product Engineer provides in-depth technical expertise in writing Physical Verification rule decks (i.e. DRC, ERC, FILL and LVS) and the usage of Physical Verification tools throughout physical implementation and signoff verification cycles.

Responsibilities:
1. Develop Physical Verification rule decks (i.e. DRC, ERC, FILL and LVS)
2. Setup efficient flows to improve rule deck development quality and product performance.
Run expert-level benchmarks and solve complex customer problems.
3. Work with the RD, field, customers and foundries to identify and define product requirement and enhancement

Position Requirements:         
1. Knowledge of developing rule decks for commercial physical verification tools (e.g. PVS, Calibre, Hercules, Dracula, Assura, etc.) is required.
2. Experience in the following areas:
- DRC, includes density, antenna, etc.
- LVS, includes device extraction, parameter measurement, connect/stamp sequences, short isolation, etc.
- Knowledge of netlist formats SPICE, CDL, Verilog, etc.
3. Experience with layout implementation tools (e.g. Virtuoso, DesignREV, ICStation, etc.) for the creation of qualification cells is required.
4. Knowledge of automating test suites for the qualification of rule decks is a plus.
5. Programming of Python, Tcl, Perl, and Skill are a plus


B.Title: Product Engineer II
Location: SH

Position Description:
1. Design and develop cutting edge technologies of Encounter/Innovus, to address future and immediate customer requirements
2. Collaborate with R&D and production validation team to deliver high quality software release
3. Provide technical support and trainings for Cadence AP business
4. Communicate with global cross-function team to create technical solutions and involve in customer engagement

Position Requirements:
1. CS/EE MS with 1+ years IC physical design experience.
2. Be familiar with IC back-end design flow, including place, route, clock tree synthesis and timing optimization.
3. Strong analysis/debug capability for technical issues.
4. Good team spirit and be able to work under pressure.
5. Good communication skill in English


C.Title: Lead Physical Design Engineer (数字后端设计项目方向)
Location: SH

Position Description:
Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. The responsibility includes participating in or leading next generation PHY IP physical design, methodology and flow development.

Position Requirements:      
BS degree with 5+ years of applicable experience, MS degree with 3+ years of applicable experience in electrical engineering, microelectronics.
Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues.
Solid knowledge on LP Design, static timing analysis, EM/IR-Drop/crosstalk analysis, physical verification, DFM.
Successful track records of taping out complex, 16nm/10nm/7nm chips. Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.
Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills in English.


D.Title: Lead Physical Design Engineer (数字后端设计Research方向)
Location: SH     

Position Description:
Co-work with the R&D RTL design team for IP architecture exploration and optimization of the design and constraint
Co-work with other functional teams (Design/STA/Analog/Package/Verification) to optimize the high speed PHY IP development flow and set proper signoff criteria.
Optimize the physical implementation methodology and flow to meet the tight timing/power target of next generation high speed PHY IP.
Set and optimize the high speed PHY IP physical implementation guide which will be used by customers and internal global physical implementation teams.   
Perform physical design implementation tasks including floor planning, place&route, clock tree synthesis and Timing/PV/Power/Signal-EM/CLP/DFM signoff checks for some critical milestone projects.
      
Position Requirements:      
BS degree with 6+ years of applicable experience, MS degree with 3+ years of applicable experience in electrical engineering, microelectronics.
Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues.
Solid knowledge on LP Design, static timing analysis, EM/IR-Drop/crosstalk analysis, physical verification, DFM.
Successful track records of taping out complex, 16nm/10nm/7nm chips.
Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.
Innovative, self-motivated, able to work independently or as a team player.
Excellent verbal and written communication skills in English.


E.Position: Title: Lead Product Engineer (数字设计流程方向)
Location: SH

Position Description:
Work with R&D and PE to enable Cadence Genus synthesis solution and Innovus implementation solution in foundry partners, and work with R&D and customers to solve high performance synthesis and implementation challenges at advanced nodes.
Develop high performance, low power and hierarchical digital reference flow from synthesis to signoff at advanced process nodes by close co-work with R&D and foundry partners. Integrate Cadence advanced technologies and up-to-date tool features into flows and solutions in foundries.
Provide technical consultant about design kit generation, library qualifications and accuracy correlation to foundries.

Position Requirements:      
BS degree with 5+ years of applicable experience, MS degree with 3+ years of applicable experience in electrical engineering, microelectronics.
Experienced with ASIC design flow, hierarchical design strategies, low power methodologies and high-performance synthesis and implementation solutions.
Good understanding in logic synthesis and logic equivalence check.
Automation and programming-minded, solid coding experience in Makefile, Tcl/Tk and Perl are plus
Good understanding advanced process nodes technology issues.
Working experience in multi-nation IC design house is preferred.
Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills in English.


F.Title: Lead Software Engineer (open to 2019 campus new graduates)
Location: SH

Key responsibilities
The candidate will be a member of the Innovus placement team in Shanghai, to work on the development and maintenance of global/detailed placement projects.

Requirements
MS/PHD from EE, computer science, math or related.
Strong software programming skill with C/C++, advanced developing and debugging capacity in Unix/Linux environment, familiar with gdb etc.
Strong problem-solving, algorithmic capacity.
Familiar with linear/nonlinear programming optimization is preferred.
Experience with script language, TCL is a plus.
EDA backend knowledge will be a strong plus.
Good verbal and written presentation are must.


G.Title: Software Engineer II (open to 2019 campus new graduates)
Location: SH

Key responsibility:
Innovus is a world-wide leading post end of line (PEOL) digital design platform. Signal router is one of the most important and challenging parts in the flow of IC design.
Nanoroute, with a successful history of two decades, is still the most robust and efficient router in the industry, supporting all the manufacturing techs even the ones still in development.
As an R&D engineer, you will have an exciting opportunity to develop the next generation routing engine.
You will work in a team environment to design, improve, and maintain core routing technology.
Surrounded by most the experienced veterans in EDA who are also willing to share, individuals with reasonable coding knowledge would grow into the top notch experts in EDA.

Position Requirements:
MS or above majored in CS/EE or similar level of expertise with 3+ years of working experience.
Coding experience on Linux platform is a plus.
Responsible and proactive team player with strong written and verbal communication skills.
Routing algorithm knowledge and experience is a plus.


H.Principal Front-end Design Engineer (RTL) （数字前端设计）
Location: SH

Position Description:
Deliver/implement DDR/HBM IP. The engineer should be able to act as a strong team member and contributor. Exercise judgment within generally defined practices and policies.
   
Specific duties include:
Proficiency in logic design, simulation
Proficiency in Verilog and its simulation environment
Good knowledge of IC design
At least seven year experience working on digital IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.

Position Requirements:
Essential Qualifications: Must have BS degree with 6~9+ years of applicable experience, MS degree with 3~6+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
Essential that the individual demonstrates strong communication, verbal and written.
Requires good communication skills in English.
Will have demonstrated successful completion of 10+ design projects as an individual contributor
Familiar with JEDEC-DDR/HBM, DFI and AMBA protocols and have DDR project design experience


I.Title: Lead Verification Engineer (数字前端验证)
Location: SH

Position Description:
Deliver/implement advanced verification solutions by utilizing Cadence’s Incisive Verification product portfolio. The engineer should be able to act as a strong team member and contributor, leading  team projects and initiatives. Exercise judgment within generally defined practices and policies.

Specific duties include:
Deep understanding on ASIC design and verification flow
Excellent knowledge of advanced verification methodology like eRM/OVM/UVM/VMM
Familiar with Cadence’s Incisive Plan to Closure Methodology (IPCM)
Proficiency in System Verilog, System C and/or e (Specman)
Developing and using Verification Components (eVC,OVC,UVC,VIP)
Developing and using assertion based verification and formal analysis methods
Skilled in scripting language, such as Perl,C shell,Python,Makefile
Assessing the project verification requirements

Position Requirements:
Essential Qualifications:
BS degree with 6+ years of applicable experience, MS degree with 3+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
Essential that the individual demonstrates strong communication, verbal and written. Requires good communication skills in English.

Desirable Qualifications:
Will have demonstrated hands-on experience and expertise with Cadence verification design tools or equivalent tools, flows and methodologies required to execute a verification project.
Will have demonstrated successful completion of 3+ verification projects as an individual contributor
Will have DDR project verification experience


J.Position: Software Engineer II for Database Development (Open to 2019 new campus graduate)
Location: SH

Job Description:
The candidate will be responsible for maintenance, development and improvement of a Cadence Database* (used by Innovus/Tempus/Voltus).

Job Requirement:
1. MS above in CS/EE or similar level of expertise with 3+ years of working experience.
2. Excellent programming skills in C/C++ on Linux/Unix platform, script (csh, Tcl etc.) programming is a plus.
3. Demonstrated problem-solving, architecture, algorithmic.
4. Good team player with strong written and verbal communication skills.
5. Strong desires to learn and explore new technologies.
6. Multi-thread programming experience is a plus.
7. EDA software development experience or IC design knowledge is a plus.

leviathanist

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leviathanist

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leviathanist

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