An Overview----ESD test methods on integrated circuits_2001

semico_ljj

ESD TEST METHODS ON INTEGRATED CIRCUITS : AN OVERVIEW

Ming-Dou Ker, Jeng-Jie Peng*, and Hsin-Chin Jiang*

Integrated Circuits & System Laboratory
Institute of Electronics
National Chiao-Tung University, Taiwan

* Analog IP Technology Section
SoC Technology Center
Industrial Technology Research Institute, Taiwan


ABSTRACT:
ESD phenomenon has become a serious
problem for IC products fabricated by deep-submicron
CMOS technologies. To qualify the ESD immunity of IC
products, there are some test methods and standards
developed by some organizations, which are ESDA,
AEC, EIA/JEDEC, and MIL-STD organizations. ESD
events have been classified into 4 models, which are
HBM, MM, CDM, and SDM. Besides, there are 4 modes
of pin combinations for ESD zapping on the IC pins,
which are specified as (1) Pin-to-VSS, (2) Pin-to-VDD,
(3) Pin-to-Pin, and (4) VDD-to-VSS. All the test
methods are designed to evaluate the ESD immunity of
IC products. The zap number, zap interval, and sample
size are all well defined in the related industrial standards.
This paper provides an overview among ESD test
methods on IC products. In general, the commercial IC
products are requested to sustain at least 2-kV HBM,
200-V MM, and 1-kV CDM ESD stresses.

liuzhieetop

:victory:

semico_ljj

Dr Ker

trentlee

very good..thank you very much

zhujun134

thanks for sharing!

eced

thank you very much

zhangxr333

不错，很好的综述

wangjm

thanks a lot

bondylep

下载看看

fujunhai119

感谢！！！