ESD protection design for CMOS integrated circuits(研討會論文—國際)

semico_ljj · 发表于 2007-10-30 13:54:40

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論文名稱 ESD protection design for CMOS integrated circuits with mixed-voltage I/O interfaces

指導教授 Ming-Dou Ker
研究生 W.-J. Chang

日期 2006 -  06 分類
B.研討會論文—國際

期刊 W.-J. Chang and Ming-Dou Ker, “ESD protection design for CMOS integrated circuits with mixed-voltage I/O interfaces,”Proc. of the 2nd Conference on Ph.D. Research in MicroElectronics and Electronics, Otranto (Lecce), Italy, Jun. 12-15, 2006, pp. 305-308

摘要       With consideration on the gate-oxide reliability, the
      new ESD protection design with ESD bus for 1.2/2.5-V mixedvoltage I/O interfaces is reported by using the new proposed high-voltage-tolerant power-rail electrostatic discharge (ESD)
      clamp circuit. This proposed power-rail ESD clamp circuit with only 1.2-V low-voltage NMOS/ PMOS devices can be operated under the 2.5-V input conditions without suffering the gate-oxide reliability issue. The experimental results in a 0.13-um CMOS process have confirmed that the proposed power-rail ESD clamp circuit has high human-body-model (HBM) and machine-model (MM) ESD robustness and fast turn-on speed. The proposed power-rail ESD clamp circuit is an excellent ESD protection solution to the mixed-voltage I/O interfaces.