各位高手对炬力ldo题目的理解？？？？

devopetent

很多人看了炬力的题以后都说简单，但是说简单的人就是不把答案写出来，
哪位高手解答一下呢？？
我想到的不多，就当抛砖引玉吧：B燥声小一些，输出管可能可以尺寸较A的小，B允许的最小vdd可能大一些，不过输出3v应该两个差别不大，因为都要大于3。   
大家想到什么说什么吧

jetboy

B图中要补偿一下
或者加个BUFFER

devopetent

原帖由 jetboy 于 2007-10-16 18:54 发表
B图中要补偿一下
或者加个BUFFER

为什么呢？两个都需要补偿没有画出吧？B有什么不同吗？

vipwl

都是单级放大器+一级调整，输出驱动能力一般（50mA的电流），电容esr合适的话，一般说来不需要额外的零点补偿。
这两个电路其实没有本质的区别，都只是一个分析的模型而已，实际电路不可能这么做。
非要说区别的话：首先，工艺上，放大器的输入对管与工艺的结合（N阱或P阱工艺）；其次，PSRR，其实这个指标很其次了，本身一级的放大器使得低频下LDO的PSRR也不会太高；再次，对调整管工作区域考察，这个基于放大器输出的摆幅范围不同，同时与调整管的尺寸一起影响着最大输出电流，以及LDO的满载与空载极端情况下的分析等等。

guangshao

个人认为第二个图的运放在直流偏置上会有问题，我反向这么多运放，没一个是这样搭配的。

mayunqi

比较深奥！！！

yefengear

ying gai hai you shen mo ba?

thomas_20005

reading this paper ,http://www.eetop.cn/bbs/viewthread.php?tid=158050&highlight=LDO%2BPSRR
you can understand the difference. The answer should be (B)

we can see that the pass device is PMOS, the PSRR is affected by two path, one is from the VDD,which is the source of PMOS.
The other one is from the preceding error amp.
The former signal path is a common-gate configuration, while the latter one is common-source configuration. Both of these two configurations have the same magnitude of signal gain, i.e. gm*rds. However, they have the opposite sign. So if the preceding error amp can pass the same power supply ripple just like that from the source of PMOS, they will cancel each other. In other words, the preceding error amp should conduct all the power supply noise without suppressing.

According to the above mentioned paper, the error amp with PMOS current-mirror connected to VDD can conduct all the power supply noise.

Similarly, if we use NMOS as pass device, it is connected as a source-follower configuration, which will pass any ripple from its gate. As a result, we need to suppress the ripple from its preceding error amp as small as possible.  Therefore, we need error amp with NMOS current mirror load here, which can suppress the power supply noise greatly.

semico_ljj

nice..