2007 CICC: 17, 18, 19

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Session 17 – Wideband Techniques

Fir Ballroom, Tuesday Afternoon, September 18

Chair:  Tony Chan Carusone

Co-Chair:  Ed Van Tuijl

This session focuses on the design of high-speed wireline circuits for data connectivity up to 100 Gb/s.  Novel architectures and methodologies are presented.

2:00 pm

Introduction

17.1  -  2:05 pm

A Heterodyne Phase Locked Loop with GHz Acquisition Range for Coherent Locking of Semiconductor Lasers in 0.13µm CMOS

F. Aflatouni, O. Momeni and H. Hashemi, USC

17.2  -  2:30 pm

A Synthesis-based Bandwidth Enhancing Technique for CML Buffers/Amplifiers

D. Pi, B.-K. Chun and P. Heydari, University of California

17.3  -  2:55 pm

Towards a sub-2.5V, 100-Gb/s Serial Transceiver (INVITED PAPER)

S. Voinigescu, R. Aroca, S. Nicolson, T. Chalvatzis, University of Toronto, P. Chevalier, P. Garcia, C. Garnier and B. Sautreuil, STMicroelectronics, T. Dickson, IBM

3:45 pm - BREAK

17.4  -  4:00 pm

Future Microprocessor Interfaces: Analysis, Design and Optimization (INVITED PAPER)

B. Casper, G. Balamurugan, J. Jaussi, J. Kennedy, M. Mansuri, F. O'Mahony and R. Mooney, Intel Corporation

17.5  -  4:50 pm

Time-Variant Characterization and Compensation of Wideband Circuits

A. Amirkhany, M. Horowitz, Stanford University, A. Abbasfar, J. Savoj, Rambus, Inc.

17.6  -  5:15 pm

High-Voltage-Tolerant I/O Circuit Design for USB 2.0-Compliant Applications

M.-J. Kim, T.H. Lee, Stanford University, H. Icking, H. Gossner, Infineon Technology

Session 18 – Compact Modeling for Analog and RF

Pine Ballroom, Tuesday Afternoon, September 18

Chair:  Rob Jones

Co-Chair:  Hong-Ha Vuong

This session presents advanced compact models and modeling/synthesis approaches to address analog and RF applications.

2:00 pm

Introduction

18.1  -  2:05 pm

PSP-Based Scalable MOS Varactor Model, (INVITED PAPER)

J. Victory, Z. Yan, J. Cordovez, Jazz Semiconductor, Z. Zhu, Q. Zhou, W. Wu, G. Gildenblat, Arizona State University, C. McAndrew, Freescale Semiconductor, F. Anderson, IBM, J. Paasschens, NXP Semiconductors, R. van Langevelde, Philips Research, P. Kolev, Qualcomm, R. Cherne, Intersil Corp. and C. Yao, Analog Devices

18.2  -  2:55 pm

An Accurate Scalable Compact Model for the Substrate Resistance of RF MOSFETs

B. Parvais, M. Dehan, A. Mercha, S. Decoutere, IMEC, S. Hu, Shanghai IC R&D Center

18.3  -  3:20 pm

Synthesis of Optimal On-Chip Baluns

S. Kapur, D. Long, R. Frye, Integrand Software, Y.-C. Chen, M.-H. Cho, H.-W. Chang, J.-H. Ou and B. Hung, UMC

3:45 pm - BREAK

18.4  -  4:00 pm

An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology

W. Wang, R. Vattikonda, Y. Cao, Arizona State University and V. Reddy, A. Krishnan, S. Krishnan, Texas Instruments

18.5  -  4:25 pm

Mismatch Characterization of Ring Oscillators

A. Balankutty, T.-C. Chih, C.-Y. Chen and P. Kinget, Columbia University

18.6  -  4:50 pm

The Advanced Compact MOSFET (ACM) Model for Circuit Analysis and Design (INVITED PAPER)

C. Galup-Montoro, M. Schneider, O. Siebel, Federal University of Santa Catarina, A. Cunha, Federal University of Bahia, F. Sousa, Federal University of Rio Grande do Norte, and H. Klimach, Federal University of Rio Grande do Sul

Session 19 – Front-Ends and Synthesizers for Communication Applications

Cedar Ballroom, Tuesday Afternoon, September 18

Chair:  Ranjit Gharpurey

Co-Chair:  Rick Carley

This session begins with presentations on four receiver front ends, covers two frequency synthesizers, and finishes with a high efficiency CMOS cellular power amplifier.

2:00 pm

Introduction

19.1  -  2:05 pm

A 3.5mW 900MHz Down-converter with Multiband Feedback and Device Transconductance Reuse

J. Han and R. Gharpurey, University of Texas Austin

19.2  -  2:30 pm

A Highly Linear Broadband Variable Gain LNA for TV Applications

D. Manstretta, Universita' degli Studi di Pavia, and L. Dauphinee, Broadcom Corp.

19.3  -  2:55 pm

A Current-Equalized Distributed Receiver Front-End for UWB Direct Conversion Receivers

A. Safarian, L. Zhou and P. Heydari, University of California Irvine

19.4  -  3:20 pm

A 65µW, 1.9 GHz RF to Digital Baseband Wakeup Receiver for Wireless Sensor Nodes

N. Pletcher, S. Gambini and J. Rabaey, University of California, Berkeley

3:45 pm - BREAK

19.5  -  4:00 pm

A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS

J. Zhuang, Q. Du and T. Kwasniewski, Carelton University

19.6  -  4:25 pm

A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop

T. Wu, Rambus Inc., P. Hanumolu, K. Mayaram and U.-K. Moon, Oregon State University

19.7  -  4:50 pm

A 1.7-GHz 31dBm differential CMOS Class-E Power Amplifier with 58% PAE

R. Brama, L. Larcher, A. Mazzanti, Universita di Modena e Reggio Emilia and F. Svelto, Universita di Pavia

casdvo

cont....

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