soc架构师、cpu、RTL、cpu验证工程师、soc设计工程师-北京、上海、苏州、成都

kevin531904

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岗位名称：SOC 架构师
地点：北京/成都
岗位职责：SOC架构的设计和系统性能评估
岗位要求：
1.硕士学位及以上，5 年以上SOC开发相关经验。
2.熟悉RTL设计，熟悉Verilog/System Verilog语言，熟悉C语言。
3.有扎实的计算机专业知识、熟悉计算机体系结构、熟悉操作系统，有服务器CPU SOC经验者优先。
4.具备多项以下一项或多项经验和知识：
a)熟悉多核SOC架构；
b)熟悉SOC片内互联子系统；
c)熟悉SOC储存子系统；
d)熟悉Chipset（南、北桥及相关I/O）；
e)熟悉Linux kernel（或其它OS）。
5.具备跨部门，大团队协作的经验。
6.良好的口头和书面沟通能力，书写技术文档的经验。


CPU设计工程师/RTL设计工程师（北京/上海）
===========================
岗位职责：
1 研发高性能服务器CPU core
2 制定处理器模块微结构设计规范
3 对性能、功耗、面积进行分析和权衡，选取优化设计方案
4 开发处理器模块RTL
5 与验证团队协作验证设计正确性
6 与物理设计团队协作实现时序收敛和功耗优化
7 与性能团队协作开发性能/功耗模拟器、模型和测试集


所需技能：
1 计算机科学、计算机工程或电子工程等相关专业学位
2 有以下至少一项经验
   - 计算机体系结构知识
   - CPU微架构知识
   - 浮点运算算法
   - CPU周期精准性能模拟器
   - Cache coherence, power management, security等领域知识
3 有工业界处理器研发经验者优先
4 良好的团队合作精神，工作态度积极








CPU Microarchitect/RTL Designer
===============================
Responsibilities:
1 Develop high-performance processor core micro-architecture targets
   server market
2 Write unit/module specification documents for the micro-architecture
3 Analyze multiple arch, uarch and circuit options to find the optimal
   design point considering power/performance/area/cost tradeoffs
4 Develop a functional block/unit RTL model then integrating and validating
5 Work with verification team to debug test failure and analysis root cause
6 Work with physical design team to fix timing issue and improve power efficience
7 Work with performance modelling team to study and tune performance bottlenecks


Qualifications
1 M.S. or B.S. in Computer Science or Computer Engineering or Electrical
   Engineering
2 Experience in at least one of following areas:
   - Computer architecture knowledge
   - Out-of-order engine
   - Floating point arithmetic
   - CPU performance modelling
   - Cache coherence, power management, security, etc
3 Industry experience in high performance CPU design is a big plus   
4 Strong communication and collaboration skills




CPU验证工程师（北京/上海/苏州）
=============
岗位职责：
1 开发处理器核、多核以及模块级验证环境
2 制定验证计划
3 开发/运行/调试测试用例以及功能覆盖点
4 使用多种验证工具、平台，例如形式化验证工具，Emulator
5 开发/维护仿真测试平台基础设施


所需技能：
1 计算机科学、计算机工程或电子工程等相关专业学位
2 有以下至少一项经验
   - 计算机体系结构知识
   - 验证环境开发，如UVM/OVM
   - 编写测试用例，开发检查器，覆盖率分析，错误调试，错误原因分析
   - 形式化验证
   - 指令集模拟器
   - 汇编语言编程，随机指令序列生成器，系统底层软件
3 熟悉以下至少一种编程语言：C/C++, Perl, Python, Ruby
4 良好的团队合作精神，工作态度积极


CPU DV Engineer
===============
Responsibilities:
You will work in fast growing team and will participate in one or several of below tasks
1 Define/develop the verification environment for the core, core submodule, and full chip
2 Create verfication test plans
3 Develop/run/debug testcases and function coverage
4 Use a wide set of verification tools and platforms, including formal verification tool, emulator
5 Develop/maintain regression infrastruction for core DV


Qualifications:
1 M.S. or B.S. in Computer Science or Computer Engineering or Electrical Engineering
2 Experience in at least one of following areas:
   - Computer architecture knowledge
   - Verification environment development in Verilog, Specman, System Verilog UVM/OVM
   - Verification and debug experience including testcase writing/generation, checker
     development, coverage analysis, failure debug, root cause analysis
   - Formal verification
   - Instruction set simulator (ISS)
   - Assembly language programming, code generation, or other low-level software experience.
3 Programming experience in at least one language: C/C++, Perl, Python, Ruby, etc.
4 Strong communication and collaboration skills






SoC数字前端逻辑设计工程师


工作地点： 北京/成都


岗位职责：
大规模SoC设计与集成、逻辑设计


岗位要求：
1.熟练掌握Verilog HDL
2.熟悉计算机体系结构, 有X86 架构经验优先
3.熟悉X86 架构 North/South bridge 的架构和设计者优先
4.熟悉PCIe/USB协议和设计者优先
5.具备SoC或者模块级验证经验
6.熟悉VCS、DC、PrimeTime等常用工具
7.具有大规模量产芯片经验优先
8.具备硬件调试能力




SoC RTL Design & Integration Architect/Engineer


Location: Beijing/Chengdu


Job Responsibility:
SoC design and integration, RTL code design


Requirements:
1. Familiar with Verilog HDL
2. Good Knowledge of computer architecture. Experience in X86 is highly preferred  
3. Familiar with AMBA protocol and Coherent Interconnect  
4. Experience in X86 North bridge & South bridge is preferred   
5. Experience in PCIe/USB protocol and design is preferred
6. Experience in SoC or module level verification is plus
7. Familiar with DC, Primetime, VCS and other EDA tools
8. Mass production experience is a plus
9. Familiar with hardware debugging and tracing

Andy126