柯明道－ESD LatchUp 最新论文8篇！！！

semico_ljj

！！！柯明道－ESD LatchUp 最新论文8篇！！！

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論文名稱	ESD protection design by using only 1xVDD low-voltage devices for mixed-voltage I/O buffers with 3xVDD input tolerance

期刊

Ming-Dou Ker and C.-T. Wang “ESD protection design by using only 1xVDD low-voltage devices for mixed-voltage I/O buffers with 3xVDD input tolerance,” Proc. of 2006 Asian Solid-State Circuits Conference (A-SSCC), Hangzhou, China, Nov. 13-15, 2006, pp. 287-290.

摘要

With a 3.3-V interface, such as PCI-X application, high-voltage overstress on the gate oxide is a serious reliability problem in designing I/O circuits by using only 1/2.5-V low-voltage devices in a 0.13- m CMOS process. Thus, a new output buffer realized with low-voltage (1- and 2.5-V) devices to drive high-voltage signals for 3.3-V applications is proposed in this paper. The proposed output buffer has been fabricated in a 0.13- m 1/2.5-V 1P8M CMOS process with Cu interconnects. The experimental results have confirmed that the proposed output buffer can be successfully operated at 133 MHz without suffering high-voltage gate-oxide overstress in the 3.3-V interface. In addition, a new level converter that is realized with only 1- and 2.5-V devices that can convert 0/1-V voltage swing to 1/3.3-V voltage swing is also presented in this paper. The experimental results have also confirmed that the proposed level converter can be operated correctly.

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[ 本帖最后由 semico_ljj 于 2007-9-7 21:53 编辑 ]

semico_ljj

論文名稱	Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process

期刊	Ming-Dou Ker, W.-Y. Chen, and K.-C. Hsu, “Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process,”IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 53, no. 10, pp. 2187-2193, Oct. 2006.
摘要	A new power-rail electrostatic discharge (ESD) clamp circuit for application in 3.3-V mixed-voltage input–output (I/O) interface is proposed and verified in a 130-nm 1-V/2.5-V CMOS process. The devices in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage nMOS/pMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V I/O interface applications. A special ESD detection circuit realized with the low-voltage devices is designed and added in the power-rail ESD clamp circuit to improve ESD robustness of ESD clamp devices by substrate-triggered technique. The experimental results verified in a 130-nm CMOS process have proven the excellent effectiveness of this new proposed power-rail ESD clamp circuit.
關鍵字	Electrostatic discharge (ESD), ESD protection circuit, high-voltage tolerant, power-rail ESD clamp circuit, substrate-triggered technique.

semico_ljj

論文名稱	Component-level measurement for transient-induced latchup in CMOS ICs under system-level ESD considerations

期刊	Ming-Dou Ker and S.-F. Hsu, “Component-level measurement for transient-induced latchup in CMOS ICs under system-level ESD considerations,” IEEE Trans. on Device and Materials Reliability, vol. 6, no. 3, pp. 461-472, Sep. 2006.
摘要	To accurately evaluate the immunity of CMOS ICs against transient-induced latch-up (TLU) under the system-level electrostatic discharge (ESD) test for electromagnetic compatibility (EMC) regulation, an efficient component-level TLU measurement setup with bipolar (underdamped sinusoidal) trigger is developed in this paper. A current-blocking diode and a currentlimiting resistance, which are generally suggested to be used in the TLU measurement setup with bipolar trigger, are investigated for their impacts to both the bipolar trigger waveforms and the TLU immunity of the device under test (DUT). All the experimental results have been successfully verified with device simulation. Finally, a TLU measurement setup without a current-blocking diode but with a small current-limiting resistance, which can accurately evaluate the TLU immunity of CMOS ICs with neither overestimation nor electrical-over-stress damage to the DUT during the TLU test, is suggested. The suggested measurement setup has been verified with silicon-controlled-rectifier test structures and real circuitry (ring oscillator) fabricated in 0.25-μm CMOS technology.
關鍵字	Holding voltage, latch-up, silicon-controlled rectifier (SCR), system-level electrostatic discharge (ESD) test, transient-induced latch-up (TLU)

semico_ljj

論文名稱	Gate-oxide reliability on CMOS analog amplifiers in a 130-nm low-voltage CMOS process

期刊

J.-S. Chen and Ming-Dou Ker, “Gate-oxide reliability on CMOS analog amplifiers in a 130-nm low-voltage CMOS process,”Proc. of 2006 International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Jul. 3-7, 2006, pp. 45-48

摘要

The effect of gate-oxide reliability in MOSFET         on common-source amplifiers is investigated with the nonstacked and stacked structures in a 130-nm low-voltage CMOS process. The supply voltage of 2.5 V is applied on the amplifiers to accelerate and observe the impact of gate-oxide reliability on circuit performances including small-signal gain,         unity-gain frequency, and output DC voltage level under DC         stress and AC stress with DC offset, respectively. The small-signal parameters of amplifier with non-stacked structure strongly degrade under such overstress conditions. The gate-oxide reliability in analog circuit can be improved by stacked structure for small-signal input and output applications

semico_ljj

論文名稱	New matching methodology of low-noise-amplifier with ESD protection

期刊

B.-S. Huang and Ming-Dou Ker, “New matching methodology of low-noise-amplifier with ESD protection,”Proc. of 2006 IEEE International Symposium on Circuits and Systems (ISCAS), Island of Kos, Greece, May 21-24, 2006, pp. 4891-4894

摘要

A new matching design of Low-Noise Amplifier (LNA) with ESD protection is proposed and implemented in an ESD-protected LNA, which manipulates the parasitic capacitance of ESD protection device as a core part of LNA matching network. Without significant degradation on RF performance, 4.5-kV Human-Body-Model (HBM) and 250-V Machine-Model (MM) ESD levels can be achieved. The low RF-performance degradation and high ESD immunity can be simultaneously realized in a simple matching structure without extra circuit components dealing with ESD parasitics in a multi-GHz LNA.

semico_ljj

論文名稱	Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask

期刊	H.-C. Hsu and Ming-Dou Ker, Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask, Proc. of 2006 IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, California, USA, March 27-29, 2006, pp. 503-506
摘要	The effect of gate-oxide reliability on MOS switch in the bootstrapped circuit is investigated with the sample-and-hold amplifier in a 130-nm CMOS process. After overstress on the MOS switch of sample-and-hold amplifier, the circuit performances in the frequency domain are measured to verify the impact of gate-oxide reliability on circuit performance.

semico_ljj

論文名稱	ESD failure mechanisms of analog I/O cells in a 0.18-um CMOS technology

期刊	Ming-Dou Ker, S.-H. Chen, and C.-H. Chuang “ESD failure mechanisms of analog I/O cells in a 0.18-um CMOS technology,” IEEE Trans. on Device and Materials Reliability, vol. 6, no. 1, pp. 102-111, Mar. 2006.
摘要	Different electrostatic discharge (ESD) protection schemes have been investigated to find the optimal ESD protection design for an analog input/output (I/O) buffer in 0.18-um 1.8- and 3.3-V CMOS technology. Three power-rail ESD clamp devices were used in power-rail ESD clamp circuits to compare the protection efficiency in analog I/O applications, namely: 1) gate-driven NMOS; 2) substrate-triggered field-oxide device, and 3) substrate-triggered NMOS with dummy gate. From the experimental results, the pure-diode ESD protection devices and the power-rail ESD clamp circuit with gate-driven NMOS are the suitable designs for the analog I/O buffer in the 0.18-um CMOS process. Each ESD failure mechanism was inspected by scanning electron microscopy photograph in all the analog I/O pins. An unexpected failure mechanism was found in the analog I/O pins with pure-diode ESD protection design under ND-mode ESD stress. The parasitic n-p-n bipolar transistor between the ESD clamp device and the guard ring structure was trggered to discharge the ESD current and cause damage under ND-mode ESD stress.
關鍵字	Analog I/O, electrostatic discharge (ESD), failure mechanism, input/output (I/O) cell, power-rail ESD clamp device

semico_ljj

論文名稱	ESD protection for mixed-voltage I/O in low-voltage thin-oxide CMOS

Ming-Dou Ker, Wei-Jen Chang, Chang-Tzu Wang, Wen-Yi Chen
National Chiao-Tung University, Hsin-Chu, Taiwan

The thickness of gate oxide in advanced CMOS technologies has
been scaled down to improve circuit operating speed. However,
the I/O circuits must drive or receive high-voltage signals to communicate
with other ICs in the microelectronic system. To solve
the gate-oxide reliability issue without using additional thick
gate oxide process [1], the stacked-NMOS configuration has been
widely used in mixed-voltage I/O interfaces [1], [2]. But, stacked-
NMOS often have much lower electrostatic discharge (ESD) level
and slower turn-on speed, as compared with single NMOS [3]. In
this work, a novel ESD protection design with a high-voltage-tolerant
power-rail ESD clamp circuit is designed to protect the
mixed-voltage I/O interfaces against ESD stresses in a 0.13μm
1.2V CMOS process.

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