Computer Organization and Design RISC-V

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Preface
About This Book
About the Other Book
Why RISC-V for This Edition?
Changes for the Fifth Edition
Instructor Support
Concluding Remarks
Acknowledgments
6
1. Computer Abstractions and Technology
Abstract
1.1 Introduction
1.2 Eight Great Ideas in Computer Architecture
1.3 Below Your Program
1.4 Under the Covers
1.5 Technologies for Building Processors and Memory
1.6 Performance
1.7 The Power Wall
1.8 The Sea Change: The Switch from Uniprocessors to
Multiprocessors
1.9 Real Stuff: Benchmarking the Intel Core i7
1.10 Fallacies and Pitfalls
1.11 Concluding Remarks
Historical Perspective and Further Reading
1.12 Historical Perspective and Further Reading
1.13 Exercises
2. Instructions: Language of the Computer
Abstract
2.1 Introduction
2.2 Operations of the Computer Hardware
2.3 Operands of the Computer Hardware
2.4 Signed and Unsigned Numbers
2.5 Representing Instructions in the Computer
7
2.6 Logical Operations
2.7 Instructions for Making Decisions
2.8 Supporting Procedures in Computer Hardware
2.9 Communicating with People
2.10 RISC-V Addressing for Wide Immediates and Addresses
2.11 Parallelism and Instructions: Synchronization
2.12 Translating and Starting a Program
2.13 A C Sort Example to Put it All Together
2.14 Arrays versus Pointers
Advanced Material: Compiling C and Interpreting Java
2.15 Advanced Material: Compiling C and Interpreting Java
2.16 Real Stuff: MIPS Instructions
2.17 Real Stuff: x86 Instructions
2.18 Real Stuff: The Rest of the RISC-V Instruction Set
2.19 Fallacies and Pitfalls
2.20 Concluding Remarks
Historical Perspective and Further Reading
2.22 Historical Perspective and Further Reading
2.22 Exercises
3. Arithmetic for Computers
Abstract
3.1 Introduction
3.2 Addition and Subtraction
3.3 Multiplication
8
3.4 Division
3.5 Floating Point
3.6 Parallelism and Computer Arithmetic: Subword Parallelism
3.7 Real Stuff: Streaming SIMD Extensions and Advanced Vector
Extensions in x86
3.8 Going Faster: Subword Parallelism and Matrix Multiply
3.9 Fallacies and Pitfalls
3.10 Concluding Remarks
Historical Perspective and Further Reading
Historical Perspective and Further Reading
3.12 Exercises
4. The Processor
Abstract
4.1 Introduction
4.2 Logic Design Conventions
4.3 Building a Datapath
4.4 A Simple Implementation Scheme
4.5 An Overview of Pipelining
4.6 Pipelined Datapath and Control
4.7 Data Hazards: Forwarding versus Stalling
4.8 Control Hazards
4.9 Exceptions
4.10 Parallelism via Instructions
4.11 Real Stuff: The ARM Cortex-A53 and Intel Core i7 Pipelines
9
4.12 Going Faster: Instruction-Level Parallelism and Matrix Multiply
Advanced Topic: An Introduction to Digital Design Using a Hardware
Design Language to Describe and Model a Pipeline and More
Pipelining Illustrations
4.13 Advanced Topic: An Introduction to Digital Design Using a
Hardware Design Language to Describe and Model a Pipeline and
More Pipelining Illustrations
4.14 Fallacies and Pitfalls
4.15 Concluding Remarks
Historical Perspective and Further Reading
4.16 Historical Perspective and Further Reading
4.17 Exercises
5. Large and Fast: Exploiting Memory Hierarchy
Abstract
5.1 Introduction
5.2 Memory Technologies
5.3 The Basics of Caches
5.4 Measuring and Improving Cache Performance
5.5 Dependable Memory Hierarchy
5.6 Virtual Machines
5.7 Virtual Memory
5.8 A Common Framework for Memory Hierarchy
5.9 Using a Finite-State Machine to Control a Simple Cache
5.10 Parallelism and Memory Hierarchy: Cache Coherence
Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive
Disks
10
5.11 Parallelism and Memory Hierarchy: Redundant Arrays of
Inexpensive Disks
Advanced Material: Implementing Cache Controllers
5.12 Advanced Material: Implementing Cache Controllers
5.13 Real Stuff: The ARM Cortex-A53 and Intel Core i7 Memory
Hierarchies
5.14 Real Stuff: The Rest of the RISC-V System and Special
Instructions
5.15 Going Faster: Cache Blocking and Matrix Multiply
5.16 Fallacies and Pitfalls
5.17 Concluding Remarks
Historical Perspective and Further Reading
5.18 Historical Perspective and Further Reading
5.19 Exercises
6. Parallel Processors from Client to Cloud
Abstract
6.1 Introduction
6.2 The Difficulty of Creating Parallel Processing Programs
6.3 SISD, MIMD, SIMD, SPMD, and Vector
6.4 Hardware Multithreading
6.5 Multicore and Other Shared Memory Multiprocessors
6.6 Introduction to Graphics Processing Units
6.7 Clusters, Warehouse Scale Computers, and Other MessagePassing Multiprocessors
6.8 Introduction to Multiprocessor Network Topologies
Communicating to the Outside World: Cluster Networking
11
6.9 Communicating to the Outside World: Cluster Networking
6.10 Multiprocessor Benchmarks and Performance Models
6.11 Real Stuff: Benchmarking and Rooflines of the Intel Core i7 960
and the NVIDIA Tesla GPU
6.12 Going Faster: Multiple Processors and Matrix Multiply
6.13 Fallacies and Pitfalls
6.14 Concluding Remarks
Historical Perspective and Further Reading
6.15 Historical Perspective and Further Reading
6.16 Exercises
Appendix
Appendix A. The Basics of Logic Design
A.1 Introduction
A.2 Gates, Truth Tables, and Logic Equations
A.3 Combinational Logic
A.4 Using a Hardware Description Language
A.5 Constructing a Basic Arithmetic Logic Unit
A.6 Faster Addition: Carry Lookahead
A.7 Clocks
A.8 Memory Elements: Flip-Flops, Latches, and Registers
A.9 Memory Elements: SRAMs and DRAMs
A.10 Finite-State Machines
A.11 Timing Methodologies
A.12 Field Programmable Devices
12
A.13 Concluding Remarks
A.14 Exercises
Appendix B. Graphics and Computing GPUs
B.1 Introduction
B.2 GPU System Architectures
B.3 Programming GPUs
B.4 Multithreaded Multiprocessor Architecture
B.5 Parallel Memory System
B.6 Floating-point Arithmetic
B.7 Real Stuff: The NVIDIA GeForce 8800
B.8 Real Stuff: Mapping Applications to GPUs
B.9 Fallacies and Pitfalls
B.10 Concluding Remarks
B.11 Historical Perspective and Further Reading
Further Reading
Appendix C. Mapping Control to Hardware
C.1 Introduction
C.2 Implementing Combinational Control Units
C.3 Implementing Finite-State Machine Control
C.4 Implementing the Next-State Function with a Sequencer
C.5 Translating a Microprogram to Hardware
C.6 Concluding Remarks
C.7 Exercises
13
Appendix D. A Survey of RISC Architectures for Desktop, Server,
and Embedded Computers
D.1 Introduction
D.2 Addressing Modes and Instruction Formats
D.3 Instructions: The MIPS Core Subset
D.4 Instructions: Multimedia Extensions of the Desktop/Server RISCs
D.5 Instructions: Digital Signal-Processing Extensions of the
Embedded RISCs
D.6 Instructions: Common Extensions to MIPS Core
D.7 Instructions Unique to MIPS-64
D.8 Instructions Unique to Alpha
D.9 Instructions Unique to SPARC v9
D.10 Instructions Unique to PowerPC
D.11 Instructions Unique to PA-RISC 2.0
D.12 Instructions Unique to ARM
D.13 Instructions Unique to Thumb
D.14 Instructions Unique to SuperH
D.15 Instructions Unique to M32R
D.16 Instructions Unique to MIPS-16
D.17 Concluding Remarks
Further Reading
Answers to Check Yourself
Chapter 1
Chapter 2
Chapter 3
14
Chapter 4
Chapter 5
Chapter 6
Glossary
Further Reading
Index
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