柯明道－Overview on ESD for mixed-voltage IO interfaces

semico_ljj

論文名稱	Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations

期刊	Ming-Dou Ker and K.-H. Lin, Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations, IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 53, no. 2, pp. 235-246, Feb. 2006
摘要	Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nano-scale CMOSprocesses. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification and analysis of ESD protection designs for mixed-voltage I/O interfaces, and the designs of high-voltage-tolerant power-rail ESD clamp circuit are presented and discussed.
關鍵字	Electrostatic discharge (ESD), ESD protection design, gate-oxide reliability, high-voltage tolerant, mixed-voltage I/O interfaces, power-rail ESD clamp circuit.

killerljj

下來看看！

sting_lover

下来看看

jingxin_xd

谢谢分享!

blinder

谢谢分享哈

lhtlht888

Best ...........

ericchen228

Ding!Ding!

bluebaby162

haohaohaohao

braudel

柯明道 juedui de quanwei

wangch010

thanks thanks