corner分pvt rc，这里的rc全称是什么

dyytx

cb

cw

rcb

rcw cw_t rcw_t 分别代表什么意思？

swary

这种没见过，一般是 Best Case，Worst Case ，Regular Case。

fengzhepianzhou

回复 1# dyytx


   r代表电阻c代表电容
b代表best
w代表worst

dmf336

RC详解
Network电容：
耦合电容：Coupling capacitance=eT/S
表面电容：Surface capcitance=eW/H
边缘电容：Fringe capcitance

决定容值的因素：
介电常数：e
线宽：W
线厚：T
线间距：S
介电材料的厚度：H

随着工艺进步，W, S, T 逐代递减，表面电容跟随减小，耦合电容随之增加，耦合电容在总电容中占比增加，当线厚 T 一定时为了减少耦合电容要么增加线间距要么减小介电常数。通常为了减小噪声敏感信号线(如clock net)上的耦合电容，在物理实现时会人为增加对应信号的线宽及线间距，俗称NDR。要减小介电常数需要从材料入手，从 .18开始引入low K介电材料。

Network电阻：
R=r/W*T, r为电阻率，除了跟线宽 W 和线厚 T 相关之外，还跟温度相关，随着温度的上升而增大

Network的单位电容和单位电阻是不可能同时最大或同时最小的。有了这些铺垫，来看一下不同工艺结点是如何定义RC corner的。
90nm 之前，Cell delay占主导，Network电容主要是对地电容，STA只需要两个RC corner即可：
Cbest(Cmin): 电容最小电阻最大
Cworst(Cmax):电容最大电阻最小
90nm 之后，netdelay的比重越来越大，而且network的耦合电容不可忽略，所以又增加了两个RC corner:
RCbest(XTALK corner): 耦合电容最大，(对地电容*电阻)最小
RCworst(Delay corner): 耦合电容最小，(对地电容*电阻)最大

至此总共有两个需要setup timing sign-off的RC corner，有四个需要hold timing sign-off的RC corner：
Setup time sign-off 的RC corner是: Cworst / RCworst
Hold time sign-off 的RC corner是: Cbest / RCbest / Cworst / RCworst

C-best:
It hasminimum capacitance. So also known as Cmin corner.
Interconnect Resistance is larger than the Typical corner.
This corner results in smallest delay for paths with short nets and can be used for min-path-analysis.

C-worst:
Refers tocorners which results maximum Capacitance. So also known as Cmax corner.
Interconnect resistance is smaller than at typical corner.
This corners results in largest delay for paths with shorts nets and can be used for max-path-analysis.

RC-best:
Refers tothe corners which minimize interconnect RC product. So also known as RC-mincorner.
Typicallycorresponds to smaller etch which increases the trace width. This results insmallest resistance but corresponds to larger than typical capacitance.
Corner has smallest path delay for paths with long interconnects and can be used for min-path-analysis.

RC-worst:
Refers tothe corners which maximize interconnect RC product. So also known as RC-maxcorner.
Typicallycorresponds to larger etch which reduces the trace width. This results inlargest resistance but corresponds to smaller than typical capacitance.
Corner has largest path delay for paths with long interconnects and can be used for max-path-analysis.

------C = a * W *L R = b *L/W RC = ab * L^2

所以对于短线来说(L很小)，RC由于与L的平方成正比，非常小，电容起主要作用。对于长线RC起主要作用。
引入的DPT(Double Patterning Technology)之后，在同一层layer上要做两次mask，两次mask之间的偏差，会导致线间距变化，从而影响耦合电容值，需要将这一因素考虑到RC corner中，所以DPT 的RC corner是：Cworst_CCworst, RCworst_CCworst, Cbest_CCbest, RCbest_CCbest

byrd2010

学习了

xiaohaolaoda

dmf336 发表于 2022-12-8 17:00
RC详解
Network电容：
耦合电容：Coupling capacitance=eT/S

非常感谢解惑