关于A10的IP验证出现TWENTYNM_FP_MAC_ENCRYPTED Ubound component问题求助

dzplay

Hi all，我在验证Altera A10的浮点加法IP过程中，出现正常输入但输出全为x的问题； 软件为vcs-mx-2014.03， log告警如下： Warning-[ELW_UNBOUND] Unbound component   The component instantiation   '/\/fp_add/fp_functions_0\/FPADDTEST_IMPL_DSP0/INST' (file:   /home/intelFPGA/16.1/quartus//eda/sim_lib/twentynm_atoms.vhd, line: 6373)   will have no effect because component 'TWENTYNM_FP_MAC_ENCRYPTED' is   unbound. No entity definition for component 'TWENTYNM_FP_MAC_ENCRYPTED' can   be found in the following libraries (  WORK  ) referenced by the   architecture 'BEHAVIOR' of entity 'TWENTYNM_FP_MAC'.   Please bind the component explicitly to an entity (architecture) pair, and   verify that the pair was analyzed successfully. $finish at simulation time                  100            V C S   S i m u l a t i o n   R e p o r t Time: 100 ps CPU Time:      0.180 seconds;       Data structure size:   0.0Mb Fri Jul  7 22:04:55 2017 初步分析该实体“twentynm_atoms.vhd”中，库已加入编译却不知为何依然报错，附上IP，欢迎高手参与讨论并帮忙分析指出问题所在。多谢！！

dzplay

已找到根因，这个是altera（intel）的quartus 16.1 std工具的问题，vhdl的仿真库存在bug故出现unbound。【临时规避方案】可使用较老的quartus（15.1）版本生成IP，对应的sim文件为另行生成的vo文件。规避了对vhdl库的调用。

hossam_fadeel