help on warning, please help

xiaoyisimonguo

I got a lot of warnings when I run "report_constraints"although they are just warning, should I ignore any of those:
Warning: No controlling value could be found for the clock gating cell 'I_ORCA_TOP/I_RISC_CORE/C12' for the clock pin 'DATA1_0'. (TIM-128)


Warning: Gated clock latch is not created for cell 'I_CLOCK_GEN/C44'on pin 'DATA1_0' in design 'ORCA'. (TIM-141)

houluhui0724

TIM-141:Wave 我们环境中会调用 set_clock_gating_check -setup 0.26 -hold 0 [all_clocks] 对所有的时钟设置了set_clock_gating_check，这样时钟传播路径上的一些组合逻辑cell（mux，与门等）触发工具推断为gating cell后，如果检测到这个pin是直接连到一个时钟，或者不是input pin，就会出现次告警；通常会出现在时钟mux上；

houluhui0724

TIM-128:Wave 。往往会和TIM-141成对出现；TIM-141针对的是gating cell的enable pin；TIM-128针对的是gating-cell的时钟pin，表示没有指出gating cell 是低通还是高通；对于时钟MUX，工具是推断不出是低通还是高通的，所以工具不会自行检查gating结果；对于AND或者NADN等简单逻辑，工具会推断是低通还是高通；