回复 20#冲出藩篱
这样应该可以吧
always@(*) //data2 64 bits
begin
if(data1[127:64] == 0)
begin
pos[6] = 1'b0;
data2 = data1[63:0];
end
else
begin
pos[6] = 1'b1;
data2 = data1[127:64];
end
end
always@(*) //data3 32 bits
begin
if(data2[63:32] == 0)
begin
pos[5] = 1'b0;
data3 = data2[31:0];
end
else
begin
pos[5] = 1'b1;
data3 = data2[63:32];
end
end
always@(*) //data4 16 bits
begin
if(data3[31:16] == 0)
begin
pos[4] = 1'b0;
data4 = data3[15:0];
end
else
begin
pos[4] = 1'b1;
data4 = data3[31:16];
end
end
always@(*) //data5 8 bits
begin
if(data4[15:8] == 0)
begin
pos[3] = 1'b0;
data5 = data4[7:0];
end
else
begin
pos[3] = 1'b1;
data5 = data4[15:8];
end
end
always@(*) //data6 4 bits
begin
if(data5[7:4] == 0)
begin
pos[2] = 1'b0;
data6 = data5[3:0];
end
else
begin
pos[2] = 1'b1;
data6 = data5[7:4];
end
end
always@(*) //data7 2 bits
begin
if(data6[3:2] == 0)
begin
pos[1] = 1'b0;
data7 = data6[1:0];
end
else
begin
pos[1] = 1'b1;
data7 = data6[3:2];
end
end
always@(*)
begin
if(data7[1] == 0)
pos[0] = 1'b0;
else
pos[1] = 1'b1;
我写了一个16位的可以试试,我仿真过了,可以的
always @ (posedge clk)begin
data_vld_d1 <= data_vld;
end
always @ (*)begin
if (data_vld) begin
data = data_in;
cnt = 'b0;
end
else begin
if (data_vld_d1) begin
if ((~data[15]) && (cnt <= 4'd15)) begin
cnt = cnt + 1;
data = data << 1;
end
else begin
end
// else begin
// end
end
end
end
always @ (posedge clk or negedge resetn)begin
if (data_vld_d1) begin
firstbit <= 4'd15 - cnt;
end
end
我谢了一个16位的,仿真过了,你可以试试
always @ (posedge clk)begin
data_vld_d1 <= data_vld;
end
always @ (*)begin
if (data_vld) begin
data = data_in;
cnt = 'b0;
end
else begin
if (data_vld_d1) begin
if ((~data[15]) && (cnt <= 4'd15)) begin
cnt = cnt + 1;
data = data << 1;
end
else begin
end
// else begin
// end
end
end
end
always @ (posedge clk or negedge resetn)begin
if (data_vld_d1) begin
firstbit <= 4'd15 - cnt;
end
end