If internal nodes are not completely pull up or down, the DC current will appear. For example, if input to inverter is HiZ, big current will appear in that inverter.
不太清楚lz讲的话, HiZ, 是high impedance的意思. 如果一个digital circuit cannot be completely pulled down/up, then both the pull-up network and pull-down network will be turned on, or at least partially turned on. This gives a direct between the two power supply rails. Therefore, it gives a high power consumption.
The conventional low speed (less than 2.5Gbps) PFD should be constructed with static logic gates. Thus, it will suffer from big current issue mentioned above.
If PFD is constructed with high speed gates (refer to 10Gbps circuits), constant bias current will be there.
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发表于 2007-6-14 15:52:45
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