科胜讯后端设计师招聘

Kidi2017

Key Areas of Responsibilities:

Physical Design for ASIC products

1 Perform floor-planning, physical synthesis, clock tree and clock gating design, power gating, routing, layout, integration and physical verification
2 Solve deep sub-micron design problems such as leakage, power, signal integrity, DFM, DFT etc.
3 Independently assess and drive complex digital physical design projects
4 Enhance IC physical design flow methodology
5 Perform power, performance and area benchmark for new technology adoption
6 Develop Perl/TCL/Shell scripts for flow and procedure automation
7 Interact with Logic designers, AMS designers and internal/external IP teams
8 Work proactively with EDA engineers and tool suppliers to debug tool functionality and bugs
9 Work with Std Cells, Memory and I/O teams
10 Support failure analysis

Required Skills and Attributes:

11 BS in Electrical Engineering, or equivalent
12 Complete knowledge of full design IC implementation and signoff process including design constraint generation, RTL Synthesis, floorplanning, cell placement, cock tree creation, SDC, routing, optimization, timing/drc closure and design signoff
13 Experienced with using Cadence Encounter, Synopsys ICC, ETS, Prime Time, PVS, QRC, Calibre, XRC, Hercules, StarRC etc.
14 Proficient in STA, power analysis, DRC/LVS/PEX/DFM, noise, static and dynamic IR drop analysis
15 Expertise in low power flow (power gating, multi-Vt, voltage islands, adaptive or dynamic voltage scaling etc)
16 Good UNIX background and Perl/Shell/SKILL scripting skills
17 Good written and verbal communication capability and proficient in both English and Mandarin
18 Strong time management and multi-tasking skills that enable on-time delivery
19 Motivated team player with customer and quality focus
20 Analytical and persistent in resolving technical issues
21 Possess strong work ethics with honesty and integrity

Preferred Skills:

1 MS, PhD in Electrical Engineering, or equivalent
2 Experienced in working with analog circuits and transistor level layout designers
3 Familiar with design and layout of logic or analog circuits using Cadence Virtuoso or other tools
4 Familiar with digital design tools such as RTL Compiler, DFT, MBIST etc.