RTL logic design help

xiaoyisimonguo

my design have these code:
`define BYTE_BURT7   3'b111
output    [7:0]    parallel_mon,
reg    [9:0]    select;      
reg    [2:0]    byteselect;


but I got the following with ncverilog run:

ncvlog: *E,NOTPAR (shiftreg4chipB.v,561|16): Illegal operand for constant expression [4(IEEE)].
  if (select[9] & (byteselect == `BYTE_BURT7 )) assign parallel_mon = reg_data[693:686];

I don't know what could have gone wrong

Please help

kketernality

`parallel_mon` is `reg` type or `wire` type?

It seems to be `reg` so that you tried to use if statement to assign the value.

You just need to remove the `assign` in the code. The value assignment in

always block does not need any `assign` in front of that.

殷工

change  if (select[9] & (byteselect == `BYTE_BURT7 ))    to   if (select[9] && (byteselect == `BYTE_BURT7 )) .   it is logic and

masaka_xlw

how come "assign" is used in this way? try :
assign parallel_mon = ((select[9] && (byteselect == `BYTE_BURT7 ))) ? reg_data[693:686] : something else