问问大家关于ISE的时序分析报告问题

yaw2009 · 发表于 2016-10-5 19:59:23

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

您需要登录才可以下载或查看，没有账号？注册

x

Minimum Data Path at Fast Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_TDO
   Location          Delay type       Delay(ns)  Physical Resource
                                                      Logical Resource(s)
   -------------------------------------------------  -------------------
   SLICE_X27Y90.AQ    Tcklo                0.235 U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL
                                                      U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC
   SLICE_X24Y90.D4    net (fanout=2)       0.216 U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL
   SLICE_X24Y90.CMUX Topdc                0.237 U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0
                                                      U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O17_F
                                                      U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O17
   SLICE_X27Y91.C3    net (fanout=1)       0.281 U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O16
   SLICE_X27Y91.C    Tilo                0.156 U_ila_pro_0/U0/I_NO_D.U_ILA/iSTAT_DOUT
                                                      U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O18
   SLICE_X27Y91.A2    net (fanout=1)       0.255 U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O17
   SLICE_X27Y91.CLK    Tah       (-Th) -0.215 U_ila_pro_0/U0/I_NO_D.U_ILA/iSTAT_DOUT
                                                      U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O115
                                                      U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_TDO
   -------------------------------------------------  ---------------------------
   Total                                     1.595ns (0.843ns logic, 0.752ns route)
                                                      (52.9% logic, 47.1% route)

问问这里的延迟类型：Tcklo、Topdc 、Tilo 、Tah为哪种类型，能给说明一下吗
还有：SLICE_X27Y90.AQ、SLICE_X24Y90.D4  、SLICE_X24Y90.CMUX、SLICE_X27Y91.C3是指SLICE的那些端口，请大神指导，能推荐点资料吗？这些事项目的问题，急急急