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BREAKDOWN OF BUNDLE AT510-BU-98000-r1p0-00rel0
This directory contains bundled deliverables from ARM. Bundled deliverables
are a way of grouping deliverables together for ease of use but which also
need to be identified separately for contractual reasons. This file shows
the breakdown of the bundled data into its constituent deliverables and
files. It is provided mainly for information for delivery tracking, but
may be useful in the event of problems being found with particular files
and tracing the origin of the files for communication with ARM's support
group.
AT510-DC-80001-r1p0-00rel0:
cortexm0_designstart/
cortexm0_designstart/Cortex_M0_DesignStart_Design_Kit_Release_Note.pdf
AT510-DC-80002-r1p0-00rel0:
cortexm0_designstart/
cortexm0_designstart/documentation/
cortexm0_designstart/documentation/DUI0926A_cortex_m0_designstart_rtl_testbench_r1p0_user_guide.pdf
AT510-MN-80001-r1p0-00rel0:
cortexm0_designstart/
cortexm0_designstart/systems/
cortexm0_designstart/systems/cortex_m0_mcu/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/generic/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/generic/config_id.h
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/generic/mcu_debugtester_interface.c
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/generic/mcu_debugtester_interface.h
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/sleep_demo/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/sleep_demo/sleep_demo_cm0.uvproj
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/sleep_demo/sleep_demo_cm0.uvopt
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/sleep_demo/makefile
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/watchdog_demo/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/watchdog_demo/watchdog_demo_cm0.uvproj
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/watchdog_demo/watchdog_demo_cm0.uvopt
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/watchdog_demo/makefile
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/default_slaves_tests/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0.uvopt
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/default_slaves_tests/default_slaves_tests_cm0.uvproj
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/default_slaves_tests/makefile
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/dualtimer_demo/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/dualtimer_demo/dualtimer_demo_cm0.uvproj
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/dualtimer_demo/dualtimer_demo_cm0.uvopt
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/dualtimer_demo/makefile
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/uart_tests/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/uart_tests/uart_tests_cm0.uvopt
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/uart_tests/uart_tests_cm0.uvproj
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/uart_tests/makefile
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/gpio_driver_tests/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/gpio_driver_tests/gpio_driver_tests_cm0.uvopt
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/gpio_driver_tests/gpio_driver_tests_cm0.uvproj
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/gpio_driver_tests/makefile
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/timer_driver_tests/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/timer_driver_tests/timer_driver_tests_cm0.uvproj
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/timer_driver_tests/timer_driver_tests_cm0.uvopt
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/timer_driver_tests/makefile
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/hello/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/hello/hello_cm0.uvopt
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/hello/hello_cm0.uvproj
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/hello/hello.c
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/hello/makefile
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/uart_driver_tests/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/uart_driver_tests/uart_driver_tests_cm0.uvproj
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/uart_driver_tests/uart_driver_tests_cm0.uvopt
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/uart_driver_tests/makefile
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/bootloader/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/bootloader/bootloader_cm0.uvopt
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/bootloader/bootloader_cm0.uvproj
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/bootloader/makefile
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/self_reset_demo/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/self_reset_demo/self_reset_demo_cm0.uvproj
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/self_reset_demo/self_reset_demo_cm0.uvopt
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/self_reset_demo/makefile
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/memory_tests/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/memory_tests/memory_tests_cm0.uvopt
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/memory_tests/memory_tests_cm0.uvproj
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/memory_tests/makefile
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/interrupt_demo/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/interrupt_demo/interrupt_demo_cm0.uvopt
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/interrupt_demo/interrupt_demo_cm0.uvproj
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/interrupt_demo/makefile
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/timer_tests/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/timer_tests/timer_tests_cm0.uvproj
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/timer_tests/timer_tests_cm0.uvopt
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/timer_tests/makefile
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/dhry/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/dhry/dhry_cm0.uvopt
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/dhry/dhry_cm0.uvproj
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/dhry/makefile
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/rtx_demo/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/rtx_demo/RTX_Config.c
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/rtx_demo/rtx_demo.c
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/rtx_demo/rtx_demo_cm0.uvopt
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/rtx_demo/rtx_demo_cm0.hex
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/rtx_demo/rtx_demo_cm0.uvproj
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/rtx_demo/makefile
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/gpio_tests/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/gpio_tests/gpio_tests_cm0.uvproj
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/gpio_tests/gpio_tests_cm0.uvopt
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/gpio_tests/makefile
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/apb_mux_tests/
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/apb_mux_tests/apb_mux_tests_cm0.uvopt
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/apb_mux_tests/apb_mux_tests_cm0.uvproj
cortexm0_designstart/systems/cortex_m0_mcu/testcodes/apb_mux_tests/makefile
cortexm0_designstart/systems/cortex_m0_mcu/rtl_sim/
cortexm0_designstart/systems/cortex_m0_mcu/rtl_sim/scripts/
cortexm0_designstart/systems/cortex_m0_mcu/rtl_sim/scripts/check_tests.pl
cortexm0_designstart/systems/cortex_m0_mcu/rtl_sim/makefile
cortexm0_designstart/systems/cortex_m0_mcu/verilog/
cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu.v
cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_clkctrl.v
cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_ahb_cs_rom_table.v
cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_system.v
cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_defs.v
cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_clkreset.v
cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_sysctrl.v
cortexm0_designstart/systems/cortex_m0_mcu/verilog/tb_cmsdk_mcu.v
cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_addr_decode.v
cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_stclkctrl.v
cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_mcu_pin_mux.v
cortexm0_designstart/systems/cortex_m0_mcu/verilog/tbench_M0_DS.vc
cortexm0_designstart/systems/cortex_m0_mcu/verilog/cmsdk_uart_capture.v
cortexm0_designstart/logical/
cortexm0_designstart/logical/models/
cortexm0_designstart/logical/models/memories/
cortexm0_designstart/logical/models/memories/cmsdk_ahb_memory_models_defs.v
cortexm0_designstart/logical/models/memories/cmsdk_ahb_ram_beh.v
cortexm0_designstart/logical/models/memories/cmsdk_ahb_ram.v
cortexm0_designstart/logical/models/memories/cmsdk_ahb_rom.v
cortexm0_designstart/logical/models/clkgate/
cortexm0_designstart/logical/models/clkgate/cmsdk_clock_gate.v
cortexm0_designstart/logical/cmsdk_ahb_gpio/
cortexm0_designstart/logical/cmsdk_ahb_gpio/verilog/
cortexm0_designstart/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_to_iop.v
cortexm0_designstart/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_gpio.v
cortexm0_designstart/logical/cmsdk_apb_subsystem/
cortexm0_designstart/logical/cmsdk_apb_subsystem/verilog/
cortexm0_designstart/logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_test_slave.v
cortexm0_designstart/logical/cmsdk_apb_subsystem/verilog/cmsdk_apb_subsystem.v
cortexm0_designstart/logical/cmsdk_apb_subsystem/verilog/cmsdk_irq_sync.v
cortexm0_designstart/logical/cmsdk_iop_gpio/
cortexm0_designstart/logical/cmsdk_iop_gpio/verilog/
cortexm0_designstart/logical/cmsdk_iop_gpio/verilog/cmsdk_iop_gpio.v
cortexm0_designstart/logical/cmsdk_ahb_default_slave/
cortexm0_designstart/logical/cmsdk_ahb_default_slave/verilog/
cortexm0_designstart/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v
cortexm0_designstart/logical/cmsdk_apb_uart/
cortexm0_designstart/logical/cmsdk_apb_uart/verilog/
cortexm0_designstart/logical/cmsdk_apb_uart/verilog/cmsdk_apb_uart.v
cortexm0_designstart/logical/cmsdk_ahb_to_apb/
cortexm0_designstart/logical/cmsdk_ahb_to_apb/verilog/
cortexm0_designstart/logical/cmsdk_ahb_to_apb/verilog/cmsdk_ahb_to_apb.v
cortexm0_designstart/logical/cmsdk_apb_dualtimers/
cortexm0_designstart/logical/cmsdk_apb_dualtimers/verilog/
cortexm0_designstart/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v
cortexm0_designstart/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_frc.v
cortexm0_designstart/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers.v
cortexm0_designstart/logical/cmsdk_apb_slave_mux/
cortexm0_designstart/logical/cmsdk_apb_slave_mux/verilog/
cortexm0_designstart/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v
cortexm0_designstart/logical/cmsdk_apb_timer/
cortexm0_designstart/logical/cmsdk_apb_timer/verilog/
cortexm0_designstart/logical/cmsdk_apb_timer/verilog/cmsdk_apb_timer.v
cortexm0_designstart/logical/cmsdk_apb4_eg_slave/
cortexm0_designstart/logical/cmsdk_apb4_eg_slave/verilog/
cortexm0_designstart/logical/cmsdk_apb4_eg_slave/verilog/cmsdk_apb4_eg_slave_interface.v
cortexm0_designstart/logical/cmsdk_apb4_eg_slave/verilog/cmsdk_apb4_eg_slave_reg.v
cortexm0_designstart/logical/cmsdk_apb4_eg_slave/verilog/cmsdk_apb4_eg_slave.v
cortexm0_designstart/logical/cmsdk_ahb_slave_mux/
cortexm0_designstart/logical/cmsdk_ahb_slave_mux/verilog/
cortexm0_designstart/logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v
cortexm0_designstart/logical/cmsdk_apb_watchdog/
cortexm0_designstart/logical/cmsdk_apb_watchdog/verilog/
cortexm0_designstart/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog.v
cortexm0_designstart/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v
cortexm0_designstart/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_frc.v
cortexm0_designstart/software/
cortexm0_designstart/software/cmsis/
cortexm0_designstart/software/cmsis/CMSIS/
cortexm0_designstart/software/cmsis/CMSIS/Include/
cortexm0_designstart/software/cmsis/CMSIS/Include/core_cm0.h
cortexm0_designstart/software/cmsis/CMSIS/Include/core_cmFunc.h
cortexm0_designstart/software/cmsis/CMSIS/Include/core_cmInstr.h
cortexm0_designstart/software/cmsis/CMSIS/Include/core_cm0plus.h
cortexm0_designstart/software/cmsis/Device/
cortexm0_designstart/software/cmsis/Device/ARM/
cortexm0_designstart/software/cmsis/Device/ARM/CMSDK_CM0/
cortexm0_designstart/software/cmsis/Device/ARM/CMSDK_CM0/Include/
cortexm0_designstart/software/cmsis/Device/ARM/CMSDK_CM0/Include/system_CMSDK_CM0.h
cortexm0_designstart/software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_driver.h
cortexm0_designstart/software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_CM0.h
cortexm0_designstart/software/cmsis/Device/ARM/CMSDK_CM0/Source/
cortexm0_designstart/software/cmsis/Device/ARM/CMSDK_CM0/Source/CMSDK_driver.c
cortexm0_designstart/software/cmsis/Device/ARM/CMSDK_CM0/Source/system_CMSDK_CM0.c
cortexm0_designstart/software/cmsis/Device/ARM/CMSDK_CM0/Source/ARM/
cortexm0_designstart/software/cmsis/Device/ARM/CMSDK_CM0/Source/ARM/startup_CMSDK_CM0.s
cortexm0_designstart/software/cmsis/Device/ARM/CMSDK_CM0/Source/GCC/
cortexm0_designstart/software/cmsis/Device/ARM/CMSDK_CM0/Source/GCC/startup_CMSDK_CM0.s
cortexm0_designstart/software/common/
cortexm0_designstart/software/common/validation/
cortexm0_designstart/software/common/validation/memory_tests.c
cortexm0_designstart/software/common/validation/uart_tests.c
cortexm0_designstart/software/common/validation/gpio_tests.c
cortexm0_designstart/software/common/validation/timer_tests.c
cortexm0_designstart/software/common/validation/default_slaves_tests.c
cortexm0_designstart/software/common/validation/uart_driver_tests.c
cortexm0_designstart/software/common/validation/apb_mux_tests.c
cortexm0_designstart/software/common/validation/gpio_driver_tests.c
cortexm0_designstart/software/common/validation/timer_driver_tests.c
cortexm0_designstart/software/common/retarget/
cortexm0_designstart/software/common/retarget/uart_stdout.c
cortexm0_designstart/software/common/retarget/retarget.c
cortexm0_designstart/software/common/retarget/uart_stdout.h
cortexm0_designstart/software/common/demos/
cortexm0_designstart/software/common/demos/watchdog_demo.c
cortexm0_designstart/software/common/demos/self_reset_demo.c
cortexm0_designstart/software/common/demos/interrupt_demo.c
cortexm0_designstart/software/common/demos/sleep_demo.c
cortexm0_designstart/software/common/demos/dualtimer_demo.c
cortexm0_designstart/software/common/bootloader/
cortexm0_designstart/software/common/bootloader/bootloader.c
cortexm0_designstart/software/common/scripts/
cortexm0_designstart/software/common/scripts/lib-nosys.ld
cortexm0_designstart/software/common/scripts/sections-nokeep.ld
cortexm0_designstart/software/common/scripts/lib-rdimon.ld
cortexm0_designstart/software/common/scripts/cmsdk_bootloader.ld
cortexm0_designstart/software/common/scripts/sections.ld
cortexm0_designstart/software/common/scripts/cmsdk_cm0.ld
cortexm0_designstart/software/common/dhry/
cortexm0_designstart/software/common/dhry/dhry_1.c
cortexm0_designstart/software/common/dhry/dhry.h
cortexm0_designstart/software/common/dhry/dhry_2.c
cortexm0_designstart/cores/
cortexm0_designstart/cores/cortexm0_designstart_r1p0/
cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/
cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/models/
cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/models/cells/
cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/models/cells/cm0_dbg_reset_sync.v
cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0_integration/
cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0_integration/verilog/
cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0_integration/verilog/cortexm0_wic.v
cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0_integration/verilog/CORTEXM0INTEGRATION.v
cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0_integration/verilog/cortexm0_rst_ctl.v
cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0_dap/
cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0_dap/verilog/
cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0_dap/verilog/CORTEXM0DAP.v
cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0ds/
cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0ds/verilog/
cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0ds/verilog/cortexm0ds_logic.v
cortexm0_designstart/cores/cortexm0_designstart_r1p0/logical/cortexm0ds/verilog/CORTEXM0DS.v
cortexm0_designstart/implementation_tsmc_ce018fg/
cortexm0_designstart/implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/
cortexm0_designstart/implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/work/
cortexm0_designstart/implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/reports/
cortexm0_designstart/implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/reports/lec/
cortexm0_designstart/implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/reports/dft/
cortexm0_designstart/implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/reports/synthesis/
cortexm0_designstart/implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/logs/
cortexm0_designstart/implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/data/
cortexm0_designstart/implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/scripts/
cortexm0_designstart/implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/scripts/cmsdk_mcu_system_reports.tcl
cortexm0_designstart/implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/scripts/cmsdk_mcu_system_tech.tcl
cortexm0_designstart/implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/scripts/cmsdk_mcu_system_clocks.tcl
cortexm0_designstart/implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/scripts/cmsdk_mcu_system_verilog.tcl
cortexm0_designstart/implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/scripts/design_config.tcl
cortexm0_designstart/implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/scripts/cmsdk_mcu_system_dft.tcl
cortexm0_designstart/implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/scripts/cmsdk_mcu_system_syn.tcl
cortexm0_designstart/implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/scripts/cmsdk_mcu_system_fm.tcl
cortexm0_designstart/implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/scripts/cmsdk_mcu_system_constraints.tcl
cortexm0_designstart/implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/scripts/cmsdk_mcu_system_verilog-rtl.tcl
cortexm0_designstart/implementation_tsmc_ce018fg/cortex_m0_mcu_system_synopsys/Makefile
m0.zip
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发表于 2016-9-20 15:32:20
谢谢