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发表于 2016-7-22 14:47:47
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显示全部楼层
- module edge_detect(
- input clk,
- input rst_n,
- input vsync,
- output reg sel
- );
- reg vsync_r1;
- always @(posedge clk or negedge rst_n)
- if(!rst_n)
- vsync_r1 <= 1'b0;
- else
- vsync_r1 <= vsync;
- wire vsync_rise = vsync && (!vsync_r1);
- always @(posedge clk or negedge rst_n)
- if(!rst_n)
- sel <= 1'b0;
- else if(vsync_rise)
- sel <= !sel;
- endmodule
复制代码
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