请教formality报error

atlandis

请教，formality出错：reference是rtl，implementation是综合出来的netlist

read_verilog -r ${RTL_SOURCE_FILES} -work_library WORK
set_top r:/WORK/${DESIGN_NAME}

read_verilog -i ${RESULTS_DIR}/${DCRM_FINAL_VERILOG_OUTPUT_FILE}
set_top i:/WORK/${DESIGN_NAME}

match

跑出来的结果报error：


Reference design is 'r:/WORK/scaler_wrapper'
Implementation design is 'i:/WORK/scaler_wrapper'
    Error: The implementation design 'i:/WORK/scaler_wrapper' is a black box. (FM-081)

***************************** Synopsys Auto Setup Summary ******************************

For further details on Synopsys Auto Setup Mode: Type man synopsys_auto_setup
****************************************************************************************

********************************* Verification Results *********************************
Verification NOT RUN

----------------------------------------------------------

atlandis

找到问题了，output写错input

Anne_xiyuan

请问，在导入implementation时，报错: input in input 是什么错呢？