always @ (posedge clk_a or negedge rst_n)
if(!rst_n)
wr_datain_r <= 8'd0;
else if((cnt_1s >= 32'd49_999_994)&&(cnt_1s <= 32'd49_999_999))
begin
timer1s <= 1;
case (i)
0: begin wr_datain_r <= Data_out [ 7:0]; i <= i+1; end
1: begin wr_datain_r <= Data_out [15:8]; i <= i+1; end
2: begin wr_datain_r <= Data_out [23:16]; i <= i+1; end
3: begin wr_datain_r <= Data_out [31:24]; i <= i+1; end
4: begin wr_datain_r <= Data_out [39:32]; i <= i+1; end
5: begin wr_datain_r <= Data_out [47:40]; i <= 0; end
endcase
end
else
begin
timer1s <= 0;
wr_datain_r <= 8'd0;
end