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要求DFT工作经验2年左右或以上,公司在虹口四川北路,GUC是台积电子公司,是世界领先的设计服务和IP供应商,有意向的可以联系我哈(kevin.tang@guc-asic.com),我可以内推~
职位描述:
Block/Chip level DFT feature and architecture definition
- DFT specification generation and review with customer co-work
- Implement block/chip level DC/AC SCAN, BSD, MBIST and IP macro test
- Do all verifications on DFT structures, and deliver quality production ATE patterns
- Deliver quality DFT timing constraints and support BE team timing closure
- Support ATE bring-up, and debug the ATE patterns for production flow
- Support logic scan/MBIST etc. DFT diagnosis for yield improvement
Candidate requirements:
- BSEE, MSEE is preferred
- 3-10 year project experience in DFT design implementation
- Hand-on experience in Synopsys (DFT Compiler/TetraMax/VCS) and Mentor Tessent MBIST is preferred
- Proficient user of Perl or TCL is preferred
- English communication skill |
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