请教，FPGA用双口RAM做图像降帧的问题

wudfwesker · 发表于 2016-4-12 22:00:15

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本帖最后由 wudfwesker 于 2016-4-12 22:03 编辑

用上位机显卡给的图像源，DVI输入是1024*768@75Hz的图像，往RAM中写了100行数据，用自生成的1024*768@50Hz时序读出，经VGA口输出，图像出现明显偏斜，这种情况是什么原因造成的。。。该如何解决呢，代码该如何改进。。。求大神指点

原图

降帧效果图

附上代码：

module jiangzhen(
hs_i,
vs_i,
de_i,
dvi_clk_in,
dvi_data,
CLK_OUT1,
BLANK_N,
H_S,
V_S,
data_out
);
input hs_i;
input vs_i;
input de_i;
input dvi_clk_in;
input [23:0] dvi_data;
input CLK_OUT1;
output wire BLANK_N;
output reg H_S;
output reg V_S;
output wire [23:0] data_out;
reg RST=0;
reg [10:0]cnt_11=0;
always @ (posedge CLK_OUT1)
if (cnt_11==11'd1000)
cnt_11<=cnt_11;
else
cnt_11<=cnt_11+1;
always @ (posedge CLK_OUT1)
if (cnt_11>=11'd900)
RST<=1;
else
RST<=0;
/////////帧计数器/////////
reg [1:0] frame_cnt=0;
wire [23:0] dina;
wire ena;
reg [16:0] addra =0;
reg [16:0] addrb =0;
reg vs_1,vs_2;
wire flag_1;
always @ (posedge dvi_clk_in)
begin
vs_1<=vs_i;
vs_2<=vs_1;
end
assign flag_1=vs_1&&!vs_2;
always @ (posedge dvi_clk_in)
if(!RST)
frame_cnt<=0;
else if (flag_1)
frame_cnt<=frame_cnt+1;
always@(posedge dvi_clk_in)
if(frame_cnt==2'd0)
begin
if(de_i)
begin
if(addra == 17'd102400)
addra <=17'd102400;
else
addra <= addra+1'b1;
end
else
addra <= addra;
end
else
addra <= 0;
assign ena =(frame_cnt ==2'd0)?1:0;
wire wea;
assign wea=1;
reg [23:0] dina_r;
always @(posedge dvi_clk_in)
dina_r <= dvi_data;
assign dina = dina_r;
always @(posedge CLK_OUT1)
if (V_S)
addrb <= 0;
else if(BLANK_N)
begin
if (addrb == 17'd102399)
addrb <=addrb;
else
addrb <= addrb + 1'b1;
end
//// INST_TAG_END ------ End INSTANTIATION Template ---------
Frame_cnt U1 (
.clka(dvi_clk_in), // input clka
.ena(ena), // input ena
.wea(wea), // input [0 : 0] wea
.addra(addra), // input [18 : 0] addra
.dina(dina), // input [7 : 0] dina
.clkb(CLK_OUT1), // input clkb
.enb(BLANK_N), // input enb
.addrb(addrb), // input [18 : 0] addrb
.doutb(data_out) // output [7 : 0] doutb
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
////////////1024*768@50Hz////////////
reg [10:0] H_cnt =0;
reg [10:0] V_cnt =0;
always@(posedge CLK_OUT1)
begin
if(RST ==0)
H_cnt <=0;
else if (H_cnt == 11'd1311)
H_cnt <= 0;
else
H_cnt <= H_cnt + 1'b1;
end
always@(posedge CLK_OUT1)
begin
if(RST ==0)
V_cnt <=0;
else if ((V_cnt == 11'd790)&&(H_cnt ==11'd1311))
V_cnt <= 0;
else if(H_cnt ==11'd1311)
V_cnt <= V_cnt + 1'b1;
else V_cnt <= V_cnt;
end
always@(posedge CLK_OUT1)
if((H_cnt >= 11'd0)&&(H_cnt <= 11'd103))
H_S <=0;
else
H_S <=1;
always@(posedge CLK_OUT1)
if((V_cnt >= 11'd0)&&(V_cnt <= 11'd2))
V_S <=1;
else
V_S <=0;
reg Blank_h;
reg Blank_v;
always@(posedge CLK_OUT1)
begin
if((H_cnt >= 11'd247)&&(H_cnt <= 11'd1271))
Blank_h <= 1;
else
Blank_h <= 0;
end
always@(posedge CLK_OUT1)
begin
if((V_cnt >=21)&&(V_cnt <= 789))
Blank_v <= 1;
else
Blank_v <= 0;
end
assign BLANK_N = (Blank_h&Blank_v);
endmodule

复制代码

[求助] 请教，FPGA用双口RAM做图像降帧的问题

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