MAP的时候总是会出现这个错误，导致MAP失败

勤劳的小男人

MAP的时候总是会出现这个错误，导致MAP失败，到底是什么原因导致的，我也只调用了6个BUFG啊！！！！！

ERRORlace:1368 - Automatic clock placement failed. Please attempt to analyze the global clocking required for this
   design and either lock the clock placement or area locate the logic driven by the clocks so that that the clocks may
   be placed in such a way that all logic driven by them may be routed. There are two main restrictions on clock
   placement for this architecture. The first is that only 12 of 32 clocks sourced by BUFGs may enter a region. The
   second is that all loads of a BUFH must be placed in the same region as the BUFH. For further information see the
   "Clocking Resources" section in the 7 Series FPGAs Clocking Resources User Guide.
ERRORack:1654 - The timing-driven placement phase encountered an error.

xjxmax

检查时钟管教和时钟个数

silencefpga

这个错误是因为布线的时候将本该布线在同一个region的时候放在了不同的region，检查代码？ 哪里使用的BUFH，如果bufg还有剩余，可以将其修改为BUFG，或者是进行位置约束，当前前提是在一个半部时钟资源是够的，不够的话，就需要找其他资源来代替，比如可以代替BUFH的有BUFG，BUFR等