Cadence 上海招聘电路设计软件开发/测试实习生

springyang

Cadence 上海招聘电路设计软件开发/测试实习生，欢迎广大在校生加入，有意者请将简历发至541515639@qq.com，邮件标题中请注明具体应聘职位。

1. Intern - Software Engineering for power route (Req#: 11745)

Position Description:
 This position is for a R&D engineer to assist in development and analysis of power route.
Position Requirements
 The candidates should have strong software programming skill with C/C++ on Linux/Unix platform.
 Strong desires to learn and explore new technologies and is able to demonstrate good analysis and problem solving skills
 Good communication in English and Chinese, good confidence and good self-motivation.

2. RD Intern- GUI (Req#: 12445)

Position Description:
 The candidate will be responsible for developing, maintaining and testing for GUI of Voltus. Voltus is an advanced power and rail analysis tool.
Position Requirements:
 Must be an MS/PhD candidate in CS/EE
 Be Familiar with C/C++ programming.
 Be Familiar with programming on Linux/Unix platform.
 One or more items of the following skills are expected.
 Be Familiar with GUI application development, such as Open GL, Qt, tcl/tk, X.
 IC design background especially on power and rail analysis.
 Good understanding on algorithm, such as KD Tree, HV Tree, especially on EDA.
 EDA software development experience is a plus.
 Good English communication skill, both oral and written.
 Team player

3. Intern-Product Validation for NanoRoute (Req #: 12553)

Position Description:
 This intern will work in Encounter Block Implementation Product Validation team and focus on NanoRoute. The responsibilities include:
 Assist in Cadence EDI flow development and validation
 Validate and maintain comprehensive NanoRoute unit and flow test cases for Encounter Digital implementation System.
 Develop test suites of the new features of EDI GPS functions.
Position Requirements:
 MS or excellent undergraduate
 Digital IC design knowledge is necessary, statistic timing analysis knowledge is a strong plus
 Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.
 Good communication in English and Chinese, good confidence and self-motivation.
 Commitment to work as intern for at least 6 months

4. Intern-Product Validation (Req #: 12163)

Position Description:
 Assist in Cadence hierarchical and DB areas development and validation
 Validate and maintain comprehensive hierarchical/Database unit and flow test cases for Encounter Digital implementation System.
 Develop test suites of the new features of hierarchical and Database functional/flow solution.
Position Requirements:
 MS or excellent undergraduate
 Digital IC design knowledge is necessary, statistic timing analysis knowledge is a strong plus
 Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.
 Good communication in English and Chinese, good confidence and self-motivation.

5. PV Intern for STA (Static Timing Analysis) (Req:12565)

Position Description:
This intern will work in Innovus "Timing Analysis" Validation team. The
responsibilities include:
 Assist in Cadence STA & delayCal product and engine's development and validation;
 Develop and maintain comprehensive STA test cases for Innovus System;
 Develop and maintain system and infrastructure for high productivity and efficiency with various scripting and system development techniques.
Position Requirements:
 MS or excellent undergraduate, Strong perl programming experience.
 IC design knowledge is necessary, statistic timing analysis knowledge is a strong plus
 Unix System knowledge, vi/TCL/TK/CSH will be plus
 Good communication in English and Chinese, good confidence and good self-motivation.
 Commitment to work as intern at least 4 days per week for more than 6 months

6. PV Intern for Low Power Flow (Replacement) (Req:12568)

Position Description:
This intern will work in Innovus Low Power Product Validation team. The
responsibilities include:
 Assist in Cadence low power flow development and validation
 Validate and maintain comprehensive lower power unit and flow test cases for Innovus Digital Implementation System.
 Develop test suites of the new features of Cadence's low power tool and solution
Position Requirements:
 MS or excellent undergraduate
 Digital IC design knowledge is necessary, statistic timing analysis knowledge is a strong plus
 Unix System knowledge, vi/TCL/TK

7. Intern-Software Engineering (Req #: 12673)

Position Description:
 The position is responsible for designing, implementing and maintaining software and algorithms related to IR Drop analysis. The engineer must have a proven ability to learn from work and work with a cross-functional team to deliver innovative products.
Position Requirements:
 MS degree candidate majored in Computer Science or Electrical Engineering
 Skilled in C/C++ programming

springyang

update

springyang

update