synopsy官网上推荐的关于sdc的书籍Constraining Designs for Synthesis and Timing

annbeasaba

thank

realhero

顶一个

cmc1023

谢谢11111

slash1221

kan kan

mk12363

非常經典的一部書

zlocoroco

谢谢，学习一下~

henry_g

学习入门一下

win3000

讲的还是比较详细的，列一下目录，为还没下载的各位做个参考：

1 Introduction ............................................................................................... 1
1.1 ASIC Design Flow ........................................................................... 1
1.2 FPGA Design Flow .......................................................................... 4
1.3 Timing Constraints in ASIC and FPGA Flow ................................. 7
1.4 Timing Constraint Issues in Nanometer Design .............................. 7
1.5 Conclusion ....................................................................................... 8
2 Synthesis Basics ......................................................................................... 9
2.1 Synthesis Explained ......................................................................... 9
2.2 Role of Timing Constraints in Synthesis ......................................... 10
2.3 Commonly Faced Issues During Synthesis ...................................... 13
2.4 Conclusion ....................................................................................... 15
3 Timing Analysis and Constraints ............................................................ 17
3.1 Static Timing Analysis ..................................................................... 17
3.2 Role of Timing Constraints in STA ................................................. 19
3.3 Common Issues in STA .................................................................... 22
3.4 Delay Calculation Versus STA ......................................................... 26
3.5 Timing Paths .................................................................................... 26
3.6 Setup and Hold ................................................................................. 29
3.7 Slack ................................................................................................. 31
3.8 On-Chip Variation ............................................................................ 32
3.9 Conclusion ....................................................................................... 33
4 SDC Extensions Through Tcl .................................................................. 35
4.1 History of Timing Constraints ......................................................... 35
4.2 Tcl Basics ......................................................................................... 36
4.3 SDC Overview ................................................................................. 41
4.4 Design Query in SDC ...................................................................... 44
4.5 SDC as a Standard ........................................................................... 44
4.6 Conclusion ....................................................................................... 46
5 Clocks ......................................................................................................... 47
5.1 Clock Period and Frequency ............................................................ 47
5.2 Clock Edge and Duty Cycle ............................................................. 48
5.3 create_clock ..................................................................................... 50
5.4 Virtual Clocks .................................................................................. 54
5.5 Other Clock Characteristics ............................................................. 54
5.6 Importance of Clock Specifi cation ................................................... 54
5.7 Conclusion ....................................................................................... 55
6 Generated Clocks ...................................................................................... 57
6.1 Clock Divider ................................................................................... 57
6.2 Clock Multiplier ............................................................................... 58
6.3 Clock Gating .................................................................................... 58
6.4 create_generated_clock .................................................................... 60
6.5 Generated Clock Gotchas ................................................................ 68
6.6 Conclusion ....................................................................................... 68
7 Clock Groups ............................................................................................. 71
7.1 Setup and Hold Timing Check ......................................................... 71
7.2 Logically and Physically Exclusive Clocks ..................................... 75
7.3 Crosstalk .......................................................................................... 76
7.4 set_clock_group ............................................................................... 78
7.5 Clock Group Gotchas ....................................................................... 80
7.6 Conclusion ....................................................................................... 80
8 Other Clock Characteristics .................................................................... 81
8.1 Transition Time ................................................................................ 81
8.2 set_clock_transition ......................................................................... 82
8.3 Skew and Jitter ................................................................................. 83
8.4 set_clock_uncertainty ...................................................................... 84
8.5 Clock Latency .................................................................................. 87
8.6 set_clock_latency ............................................................................. 88
8.7 Clock Path Unateness ...................................................................... 90
8.8 set_clock_sense ................................................................................ 91
8.9 Ideal Network ................................................................................... 93
8.10 Conclusion ....................................................................................... 94
9 Port Delays ............................................................................................... 95
9.1 Input Availability ........................................................................... 95
9.2 Output Requirement ....................................................................... 98
9.3 set_input_delay .............................................................................. 101
9.4 set_output_delay ............................................................................ 106
9.5 Relationship Among Input and Output Delay ............................... 108
9.6 Example Timing Analysis .............................................................. 110
9.7 Negative Delays ............................................................................. 114
9.8 Conclusion ..................................................................................... 114
10 Completing Port Constraints .................................................................. 117
10.1 Drive Strength ................................................................................ 117
10.2 Driving Cell.................................................................................... 119
10.2.1 set_driving_cell ................................................................ 120
10.3 Input Transition .............................................................................. 125
10.4 Fanout Number .............................................................................. 126
10.5 Fanout Load ................................................................................... 126
10.6 Load ............................................................................................... 127
10.7 Conclusion ..................................................................................... 129
11 False Paths ................................................................................................ 131
11.1 Introduction .................................................................................... 131
11.2 set_false_path ................................................................................. 131
11.3 Path Specifi cation ........................................................................... 132
11.4 Transition Specifi cation ................................................................. 135
11.5 Setup/Hold Specifi cation ............................................................... 137
11.6 Types of False Paths ....................................................................... 137
11.7 set_disable_timing ......................................................................... 142
11.8 False Path Gotchas ......................................................................... 143
11.9 Conclusion ..................................................................................... 144
12 Multi Cycle Paths ..................................................................................... 145
12.1 SDC Command for Multi Cycle Paths ........................................... 145
12.2 Path and Transition Specifi cation................................................... 146
12.3 Setup/Hold Specifi cation ............................................................... 147
12.4 Shift Amount .................................................................................. 148
12.5 Example Multi Cycle Specifi cation ............................................... 151
12.6 Conclusion ..................................................................................... 155
13 Combinational Paths ............................................................................... 157
13.1 set_max_delay ................................................................................ 157
13.2 set_min_delay ................................................................................ 158
13.3 Input/Output Delay ........................................................................ 158
13.4 Min/Max Delay Versus Input/Output Delay .................................. 161
13.5 Feedthroughs .................................................................................. 162
13.6 Point-to-Point Exception ................................................................ 164
13.7 Path Breaking ................................................................................. 165
13.8 Conclusion ..................................................................................... 166
14 Modal Analysis .........................................................................................  167
14.1 Usage Modes .................................................................................. 167
14.2 Multiple Modes .............................................................................. 167
14.3 Single Mode Versus Merged Mode ................................................ 169
14.4 Setting Mode .................................................................................. 169
14.5 Other Constraints ........................................................................... 172
14.6 Mode Analysis Challenges ............................................................ 172
14.7 Confl icting Modes .......................................................................... 173
14.8 Mode Names .................................................................................. 175
14.9 Conclusion ..................................................................................... 175
15 Managing Your Constraints .................................................................... 177
15.1 Top-Down Methodology ................................................................ 177
15.2 Bottom-Up Methodology ............................................................... 178
15.3 Bottom-Up Top-Down (Hybrid) Methodology .............................. 181
15.4 Multimode Merge .......................................................................... 183
15.5 Challenges in Managing the Constraints ....................................... 190
15.6 Conclusion ..................................................................................... 192
16 Miscellaneous SDC Commands .............................................................. 193
16.1 Operating Condition ....................................................................... 193
16.2 Units ............................................................................................... 197
16.3 Hierarchy Separator ....................................................................... 198
16.4 Scope of Design ............................................................................. 200
16.5 Wire Load Models ......................................................................... 201
16.6 Area Constraints ............................................................................. 204
16.7 Power Constraints .......................................................................... 205
16.8 Conclusion ..................................................................................... 207
17 XDC: Xilinx Extensions to SDC ............................................................. 209
17.1 Clocks ............................................................................................ 209
17.2 Timing Exceptions ......................................................................... 216
17.3 Placement Constraints .................................................................... 217
17.4 SDC Integration in Xilinx Tcl Shell .............................................. 218
17.5 Conclusion ..................................................................................... 218

刺客无痕

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luminate

repeat (32) thank you very much