asic PM & PD-芯得20160118

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Position: Senior Manager or Director, depending upon qualification, ofSOC Design

简历发 [url=mailtoffer@hi-talent.net]offer@hi-talent.net[/url]

Job Description:

(1)   Lead a SOC design team thatincludes IC architecture, logic design, integration, verification, andvalidation.

(2)   Provide technicalconsultation and resolve technical issues on product development.

(3)   Work with MKT for productdefinition, SE for system design, SW for verification and validation

(4)   Lead tasks related to ICproduction, including issue debugging, bug fix, and solution.

Job Requirement

•     Fluent in Verilog, Familiar with System Verilog and/or System C

•     Familiar with C language. Knowledge of scripting languages is a plus.

•     Intimate knowledge on SOC architecture

•     Familiar with RISC architecture and bus protocols such as AXI and AHB

•     Intimate knowledge on bus arbitration for SOC design

•     Familiar with FPGA prototype verification flow

•     Knowledge of SOC peripheral modules such as flash controller, DDR controller,AV interfaces (HDMI, CVBS, YPbPr, I2S, S/PDIF)

•     Knowledge of audio and video technology

•     Experience on large-scale emulator system (Veloce and/or Palladium)

•     Master degree with at least 10 years of IC development experience

•     Successful IC tape-out in 40 nm or more advanced processes

•     Proven track record of large-scale SOC production

Senior Digital Manager 简历发 [url=mailtoffer@hi-talent.net]offer@hi-talent.net[/url]

Job description:

- Conduct technical feasibilityanalysis,  define chip micron architecture and module spec’s;

- Work with analog design lead for newproduct development project planning and tracking;

- Design, implementation, and verificationof digital in mixed-signal ICs;

- Perform backend digital design (logicsynthesis, formal check, define design constraints for place and route, performtiming closure, DFT)

- Script based synthesis & timinganalysis on GHz working frequency

- Support system, test and product teamwith chip debugging, failure analysis, characterizations and product releaseefforts

Requirements:

- PH.D or MSEE with minimum 10-year designand project lead experience of mixed-signal chip development experience

- Solid knowledge and design experience invery high speed SoC with embedded MPU

- Projects tape out experience with 65nmprocess, 40nm or 28nm

- Relevant experience on DDR/Serdesinterface is a plus

- Solid knowledge of high-speedsynchronous/asynchronous circuit design, family with standard cell architectureand behavior

- Family with low-power-design flow andtechniques

- Strong skills of Verilog RTL coding,verification and debug

- Hands on experience in EDA tools such asCadence NC-Sim, Synopsys DC, PT, etc.

- Solid knowledge of documentation ofdesign report

- Highly organized and self motivated

- Ability to plan and  manage a projectand effectively drive team’s execution

职位：高级经理或主管，根据资格，对系统芯片设计

简历发 [url=mailtoffer@hi-talent.net]offer@hi-talent.net[/url]  

职位描述：

（1）领导一个设计团队，包括集成电路结构，逻辑设计，集成，验证和验证。

（2）为产品开发提供技术咨询和解决技术问题。

（3）与市场部进行产品定义的工作，本身的系统设计，软件验证和确认

（4）与集成电路生产相关的领导任务，包括发行调试、缺陷修补和解决方案。

岗位需求

•精通Verilog，熟悉System Verilog和/或系统C

熟悉c++语言。熟悉脚本语言优先。

在片上系统结构方面的知识

•熟悉RISC体系结构和总线协议如AXI、AHB

在汽车上的设计中，对总线仲裁的认识

•熟悉FPGA原型验证流程

•知识SOC外围模块如闪存控制器，DDR控制器、AV接口（HDMI、CVBS、YPbPr、I2S和S/PDIF）

音频和视频技术知识

•大型仿真系统的经验（快速和/或钯）

硕士学位至少10年的集成电路开发经验

在40纳米或更先进的过程中成功地集成电路磁带

大型片上生产记录的证明记录

高级经理简历发     offer@hi-talent.net   

职位描述：

•进行技术可行性分析，定义芯片微米结构和模块规格；

•工作与模拟设计，导致新产品开发项目的规划和跟踪；

数字混合信号集成电路的设计、实现和验证；

执行后端数字设计（逻辑综合、形式验证、确定地点和路线，设计约束执行定时关闭，DFT）

基于脚本的工作频率合成与时序分析

•支持系统、测试和产品团队与芯片的调试、故障分析、表征及产品发布工作

要求：

-博士或硕士至少10年设计和混合信号芯片开发经验项目领导经验

固与嵌入式微处理器的高速SOC设计经验知识

项目带了65nm工艺经验，40nm或28nm

在DDR/ SERDES接口有相关经验

•扎实的高速同步/异步电路设计知识，有标准的细胞结构和行为

•低功耗设计流程和技术

较强的RTL编码能力，验证和调试

对EDA工具，如Cadence NC SIM，Synopsys DC，PT的经验等。

•扎实的设计报告文档

•高度组织能力和自我激励

•能够计划和管理项目，并有效地推动团队的执行

Staff/Senior Staff /    Physical Design Engineer

简历发 hr@hi-talent.com微信 xinde_jane  

Location : China  

Designation:

Senior Design Engineer / Staff DesignEngineer

Experience Level:

6- 12 years of hands-on physical designexperience

Responsibilities:

•Responsibilitieswill include block level ownership of design, unit level verification, designreviews.

•Workwith multiple sites in a team environment particularly with offices in the US.

  Requirements:

•BS /MS in EE/CSE from a reputed University.

•Goodknowledge of EDA tools from Synopsys, Cadence and Mentor required. Inparticular experience with PTSI, Innovus, First Encounter, Nanoroute, Calibre,StarRC, and Conformal is essential.

•Goodknowledge of VLSI process and device characteristics, to make optimal trade-offbetween performance and power.

•Goodknowledge of standard cell libraries – circuit design and cell layout.

•Goodunderstanding of static timing analysis (STA), EM/IR and sign-off flows.

•Stronghands-on experience with:

•Lowpower design techniques.

•Floorplanning, place & route, power and clock distribution, pin placement andtiming constraints generation.

•Timingconvergence using high speed design techniques with signal integrity &EM/IR.

•Physicaldesign verification.

•Functionalverification at various levels of design hierarchy with respect to golden RTLby formal methods.

•Priorexperience with 16nm, 28nm or finer geometries.

•Goodsoftware and scripting skills (perl, python, tcl).

•Self-drivenindividual and an excellent team player experienced in working with remoteteams.

•Musthave good communication skills and the ability and desire to work as a team.

Job Description

•Candidateis expected to work on RTL to GDS for processor core designs, optimizing theimplementations for power, timing and area.

•Tobe responsible for and own all aspects of physical design and physicalverification effort at a block level. Will also need to help out at the toplevel.

•Develop,support and maintain physical design flows and methodologies.

•Workclosely with the design team to accomplish the objectives.

Essential Requirements  

•Expertin physical design of high frequency chips with emphasis on successful timingclosure.

•Excellentunderstanding of geometry/ process/ device technology implications on physicaldesign.

•Expertin physical design verification.

•Independent, self-driven, strong team player.

员工/高级员工/物理设计工程师

简历发 hr@hi-talent.com微信xinde_jane

地点：中国

称号：

高级设计工程师/设计工程师

经验水平：

12 - 6年的实际设计经验

责任：

责任包括：设计、单位级验证、设计评审的分块级所有权。

在一个团队环境中工作多个网站，特别是在美国的办公室。

要求：

•学士/硕士EE / CSE从著名大学。

•EDA工具Synopsys Cadence和Mentor需要良好的知识。与PtSi，特定经历Innovus，第一次遇到，汇编，口径，starrc，形是必不可少的。

良好的集成电路工艺和设备特性，以使性能和功率之间的最佳折衷。

熟悉标准单元库，电路设计和单元布局。

•静态时序分析（STA）了解，EM / IR和签字流程。

有较强的实践经验：

低功耗设计技术。

·地板计划，地点和路线，电源和时钟分配，销位置和时间约束的产生。

利用信号完整性和电磁/红外高速设计技术的定时收敛性。

物理设计验证。

•功能验证在不同层次的设计层次，通过形式化的方法对黄金RTL。

•经验与16nm，28nm或精细的几何形状。

•好软件和脚本编写能力（Perl、Python、Tcl）。

自我导向的个人和一个优秀的团队合作，有经验的工作与远程团队。

必须有良好的沟通能力和团队合作能力。

职位描述

•候选人工作预计将在处理器核心的设计，GDS的RTL，权力实现优化、时序和面积。

在一个块级负责和自己的物理设计和物理验证工作的所有方面。还需要在高层帮助。

开发、支持和维护物理设计流程和方法。

与设计团队紧密合作，完成目标。

本质要求

在高频芯片物理设计方面的专家，重点是成功的定时关闭。

·对物理设计的几何/工艺/设备技术有很好的理解。

在物理设计验证专家。

独立的，自我驱动的，强大的团队合作精神。

Best Regards

Jane.Jin 金娟

Principal Consultant & General Manager @ Hi-TalentConsulting Co.,Ltd.

上海芯得企业管理咨询有限公司

上海芯相会企业管理咨询有限公司

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