【NVIDIA招聘】ASIC Timing Engineer -上海

NVHR

Hi All,

这边是NVIDIA HR Tracy, 我们目前在上海招聘 ASIC Timing Engineer , 具体职位描述如下，有意向的朋友，欢迎发送简历到 tracyw@nvidia.com   
QQ: 1751315121

收到简历 我会及时同你联系； 谢谢；工作地点: 上海市浦东新区 秋月路26号 （靠近地铁2号线 广兰路站）

The NVIDIA Clocks group is looking for an ASIC engineer with extensive experience in high-speed logic design and timing. The complexity of clocking structure has grown substantially in order to support high frequency clock domains. Modern clocking design needs to balance high frequency clocks with power, DFT, noise, circuit and physical design constraints.

Responsibilities:
- Perform Synthesis & STA on the designed high speed clock logics.
- Constraint setup and validation in standard & in-house tool flow
- Work in conjunction with Place and Route Engineers to achieve timing closure
- Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers/switchs, OCC & IO macros interfaces
- Develop scripts for performing ECO's.
- Develop and enhance entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
MINIMUM REQUIREMENTS:

-        BS / MS in electrical / computer engineering and related.
-        Above 2 years of relevant ASIC experience ideally with a focus in the chip timing/synthesis/formal closure
-        Excellent TCL/Perl scripts skills
-        Excellent analytical and problem solving skills
-        Fluent English (both written and spoken) and excellent communication skills
-        Ability to multiplex many issues, set priorities, and work in a team environment
-        Keep up to date with leading edge technologies

Best Regards
Tracy