1. pt读入Verilog时出现以下warning
Warning:Module 'FSUBC_0' in file '/home/final.v' is not used in the current design
Warning:Module 'FSUBC_1' in file '/home/final.v' is not used in the current design
.......
Warning:Module 'LATCHin 8_0' file '/home/final.v' is not used in the current design
==>请问是什么原因产生的?
2. pt读入spef时出现以下大量error
Error:Cannot find port/pin 'U2/START_STOP/U101/A' in design 'SPI_PCM'
Error:Cannot find port/pin 'U2/START_STOP/U101/N18496' in design 'SPI_PCM'
......
Error:Cannot resolve net ''U2/START_STOP/U101/N15042'
==>请问是什么原因产生的?如何解决?