##################################################
## ##
## C A L I B R E S Y S T E M ##
## ##
## L V S R E P O R T ##
## ##
##################################################
REPORT FILE NAME: 2.lvs.report
LAYOUT NAME: /home/cds/edalab/2.sp ('2')
SOURCE NAME: /home/cds/edalab/2.src.net ('2')
RULE FILE: /home/cds/edalab/_1830AN18BA_CAL_3M_270.lvs_
CREATION TIME: Tue Dec 15 20:47:54 2015
CURRENT DIRECTORY: /home/cds/edalab
USER NAME: cds
CALIBRE VERSION: v2008.1_20.15 Tue Mar 4 19:02:13 PST 2008
LVS COMPONENT TYPE PROPERTY phy_comp element comp
LVS COMPONENT SUBTYPE PROPERTY phy_model
LVS PIN NAME PROPERTY phy_pin
LVS POWER NAME "vdd"
LVS GROUND NAME "vss"
LVS CELL SUPPLY NO
LVS RECOGNIZE GATES ALL
LVS IGNORE PORTS NO
LVS CHECK PORT NAMES YES
LVS IGNORE TRIVIAL NAMED PORTS NO
LVS BUILTIN DEVICE PIN SWAP NO
LVS ALL CAPACITOR PINS SWAPPABLE NO
LVS DISCARD PINS BY DEVICE NO
LVS SOFT SUBSTRATE PINS NO
LVS INJECT LOGIC YES
LVS EXPAND UNBALANCED CELLS YES
LVS EXPAND SEED PROMOTIONS NO
LVS PRESERVE PARAMETERIZED CELLS NO
LVS GLOBALS ARE PORTS YES
LVS REVERSE WL NO
LVS SPICE PREFER PINS NO
LVS SPICE SLASH IS SPACE YES
LVS SPICE ALLOW FLOATING PINS YES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGS NO
LVS SPICE CONDITIONAL LDD YES
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
LVS SPICE IMPLIED MOS AREA NO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALS NO
LVS SPICE REDEFINE PARAM NO
LVS SPICE REPLICATE DEVICES YES
LVS SPICE STRICT WL NO
// LVS SPICE OPTION
LVS STRICT SUBTYPES NO
LAYOUT CASE YES
SOURCE CASE YES
LVS COMPARE CASE NO
LVS DOWNCASE DEVICE NO
LVS REPORT MAXIMUM 50
LVS PROPERTY RESOLUTION MAXIMUM 32
// LVS SIGNATURE MAXIMUM
LVS FILTER UNUSED OPTION AB O RB RC RD RE RG
// LVS REPORT OPTION
LVS REPORT UNITS YES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// Device Type Map
LVS DEVICE TYPE PMOS "pch_eprom_5p0v_pgm" SOURCE LAYOUT
LVS DEVICE TYPE NMOS "nch_svt_5p0v" SOURCE LAYOUT
LVS DEVICE TYPE NMOS "nch_lvt_5p0v" SOURCE LAYOUT
LVS DEVICE TYPE NMOS "nch_svt_iso_5p0v" SOURCE LAYOUT
LVS DEVICE TYPE NMOS "nch_ee_5p0v_pgm" SOURCE LAYOUT
LVS DEVICE TYPE NMOS "nch_ee_5p0v_to_pgm" SOURCE LAYOUT
LVS DEVICE TYPE NMOS "nch_ee_dp_5p0v_pgm" SOURCE LAYOUT
LVS DEVICE TYPE NMOS "nch_dvt_5p0v" SOURCE LAYOUT
LVS DEVICE TYPE NMOS "nch_dvt_iso_5p0v" SOURCE LAYOUT
LVS DEVICE TYPE LDDNMOS "nch_dea_7v" SOURCE LAYOUT
LVS DEVICE TYPE LDDNMOS "nch_dea_iso_7v" SOURCE LAYOUT
LVS DEVICE TYPE LDDNMOS "nch_dea_12v" SOURCE LAYOUT
LVS DEVICE TYPE LDDNMOS "nch_dea_20v" SOURCE LAYOUT
LVS DEVICE TYPE LDDNMOS "nch_dea_24v" SOURCE LAYOUT
LVS DEVICE TYPE LDDNMOS "nch_dea_30v" SOURCE LAYOUT
LVS DEVICE TYPE LDDNMOS "nch_io_5p0v_4t" SOURCE LAYOUT
LVS DEVICE TYPE LDDNMOS "nch_pp_5p0v_4t" SOURCE LAYOUT
LVS DEVICE TYPE LDDNMOS "nch_io_iso_5p0v_6t" SOURCE LAYOUT
LVS DEVICE TYPE LDDNMOS "nch_pp_iso_5p0v_6t" SOURCE LAYOUT
LVS DEVICE TYPE LDDNMOS "nch_dea_dvt_24v" SOURCE LAYOUT
LVS DEVICE TYPE PMOS "pch_svt_5p0v" SOURCE LAYOUT
LVS DEVICE TYPE PMOS "pch_svt_iso_5p0v" SOURCE LAYOUT
LVS DEVICE TYPE PMOS "pch_des_ftr_20v" SOURCE LAYOUT
LVS DEVICE TYPE LDDPMOS "pch_dea_7v" SOURCE LAYOUT
LVS DEVICE TYPE LDDPMOS "pch_dea_12v" SOURCE LAYOUT
LVS DEVICE TYPE LDDPMOS "pch_dea_20v" SOURCE LAYOUT
LVS DEVICE TYPE LDDPMOS "pch_dea_24v" SOURCE LAYOUT
LVS DEVICE TYPE LDDPMOS "pch_dea_30v" SOURCE LAYOUT
LVS DEVICE TYPE LDDPMOS "pch_io_5p0v_5t" SOURCE LAYOUT
LVS DEVICE TYPE LDDPMOS "pch_io_iso_5p0v_5t" SOURCE LAYOUT
LVS DEVICE TYPE LDDPMOS "esd_hv_12v_prim" SOURCE LAYOUT
LVS DEVICE TYPE LDDPMOS "esd_hv_24v_prim" SOURCE LAYOUT
LVS DEVICE TYPE DIODE "dio_stk_24v" SOURCE LAYOUT
LVS DEVICE TYPE DIODE "dio_stk_30v" SOURCE LAYOUT
LVS DEVICE TYPE DIODE "nch_io_5p0v" [ POS=D NEG=GSB ] SOURCE LAYOUT
LVS DEVICE TYPE DIODE "nch_pp_5p0v" [ POS=D NEG=GSB ] SOURCE LAYOUT
LVS DEVICE TYPE DIODE "pch_io_5p0v" [ POS=D NEG=GSB ] SOURCE LAYOUT
LVS DEVICE TYPE DIODE "esd_hv_pig_7v" [ POS=D NEG=GSB ] SOURCE LAYOUT
LVS DEVICE TYPE DIODE "esd_hv_iso_pig_7v" [ POS=D NEG=GSB ] SOURCE LAYOUT
// Reduction
LVS REDUCE SERIES MOS NO
LVS REDUCE PARALLEL MOS YES [ TOLERANCE length 0 ]
LVS REDUCE SEMI SERIES MOS NO
LVS REDUCE SPLIT GATES NO
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE SERIES CAPACITORS NO
LVS REDUCE PARALLEL CAPACITORS YES
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE PARALLEL RESISTORS NO
LVS REDUCE PARALLEL DIODES YES
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
o Statistics:
4 layout mos transistors were reduced to 2.
2 mos transistors were deleted by parallel reduction.