|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
Writing Testbenches using SystemVerilog
By Janick Bergeron
Publisher: Springer
Number Of Pages: 414
Publication Date: 2006-02-10
ISBN / ASIN: 0387292217
EAN: 9780387292212
Binding: Hardcover
Manufacturer: Springer
Studio: Springer
Average Rating: 4
Total Reviews: 1
Book Description:
Verification is too often approached in an ad hoc fashion. Visually inspecting
simulation results is no longer feasible and the directed test-case methodology
is reaching its limit. Moore's Law demands a productivity revolution in
functional verification methodology.
Writing Testbenches Using SystemVerilog offers a clear blueprint of a
verification process that aims for first-time success using the SystemVerilog
language. From simulators to source management tools, from specification to
functional coverage, from I's and O's to high-level abstractions, from
interfaces to bus-functional models, from transactions to self-checking
testbenches, from directed testcases to constrained random generators, from
behavioral models to regression suites, this book covers it all.
Writing Testbenches Using SystemVerilog presents many of the functional
verification features that were added to the Verilog language as part of
SystemVerilog. Interfaces, virtual modports, classes, program blocks, clocking
blocks and others SystemVerilog features are introduced within a coherent
verification methodology and usage model.
Writing Testbenches Using SystemVerilog introduces the reader to all elements of
a modern, scalable verification methodology. It is an introduction and prelude
to the verification methodology detailed in the Verification Methodology Manual
for SystemVerilog.
怎么网速这么慢，半天都传不动啊，哪位要是有高速的代理就好了。
[ 本帖最后由 vertyang 于 2007-5-27 12:51 编辑 ] |
-
cover
|
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2007-5-27 12:14:08
