错误如下:# ** Error: ../src/hdlc_env.sv(1): near "uvm_env": syntax error, unexpected IDENTIFIER
# ** Error: ../src/hdlc_env.sv(1): Error in class extension specification.
# ** Error: E:/modeltech_10.1a/win32/vlog failed.
hdlc_env.sv里面定义了一个这样的类:
class hdlc_env extends uvm_env;
我是通过脚本编译的,脚本内容如下:
set UVM_HOME e:/modeltech_10.1a/verilog_src/uvm-1.1d
set MODEL_TECH e:/modeltech_10.1a/win32
set PATH C:/Users/Administrator/Desktop/SV/PRJ/hdlc